专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07474672B2 Frame alteration logic for network processors 失效
标题翻译：网络处理器的帧更改逻辑
公开(公告)号：US07474672B2
公开(公告)日：2009-01-06
申请号：US10364069
申请日：2003-02-11
申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Vaidhyanathan , Johan G. A. Verkinderen
发明人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Vaidhyanathan , Johan G. A. Verkinderen
IPC分类号： H04J3/22
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/40
摘要： Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
摘要翻译：通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。帧头中的信息包含用于修改帧中的信息的帧改变命令。修改包括添加新信息，删除信息和叠加信息。变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。

2. 发明授权

US07643511B2 Frame alteration logic for network processors 失效
标题翻译：网络处理器的帧更改逻辑
公开(公告)号：US07643511B2
公开(公告)日：2010-01-05
申请号：US12327761
申请日：2008-12-03
申请人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
发明人： Peter I. A. Barri , Claude Basso , Jean L. Calvignac , Brahmanand K. Gorti , Joseph F. Logan , Natarajan Valdhyanathan , Johan G. A. Verkinderen
IPC分类号： H04J3/22
CPC分类号： H04L49/25 , H04L49/3009 , H04L49/40
摘要： Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.
摘要翻译：通信系统中的分组交换节点包括用于接收具有格式化控制块的包含报头部分的输入信息分组或帧的装置。帧头中的信息包含用于修改帧中的信息的帧改变命令。修改包括添加新信息，删除信息和叠加信息。变更引擎中的解码器和控制装置解释命令并对帧数据应用修改。存储通用和标准数据模式用于插入或覆盖以节省数据分组空间。

3. 发明授权

US07283529B2 Method and system for supporting a dedicated label switched path for a virtual private network over a label switched communication network 有权
标题翻译：用于在标签交换通信网络上支持用于虚拟专用网络的专用标签交换路径的方法和系统
公开(公告)号：US07283529B2
公开(公告)日：2007-10-16
申请号：US10383973
申请日：2003-03-07
申请人： Claude Basso , Brahmanand K. Gorti , Natarajan Vaidhyanathan , Colin B. Verrilli
发明人： Claude Basso , Brahmanand K. Gorti , Natarajan Vaidhyanathan , Colin B. Verrilli
IPC分类号： H04L12/28 , H04L12/56 , G06F15/173
CPC分类号： H04L45/54 , H04L12/4641 , H04L45/50
摘要： A system and method for transmitting data from a first site to a second site over a shared Multi-Protocol Label Switched (MPLS) network comprising a plurality of routers, including an ingress router in communication with the first site and an egress router in communication with the second site, includes configuring a plurality of label switching paths between the ingress router and the egress router over a plurality of label switching devices. The method further includes performing a first lookup on one of at least one virtual routing and forwarding (VRF) table stored in the ingress router, whereby the first lookup identifies one routing table from a plurality of routing tables stored in the ingress router, each routing table being associated with one of the plurality of label switched paths, and performing a second lookup on the one routing table, wherein the routing table defines the associated label switched path between the ingress router and the egress router for a virtual private network (VPN) between the first site and the second site.
摘要翻译：一种用于通过共享的多协议标签交换（MPLS）网络从第一站点传送数据到第二站点的系统和方法，包括多个路由器，包括与第一站点通信的入口路由器和与第一站点通信的出口路由器第二站点包括通过多个标签交换设备在入口路由器和出口路由器之间配置多个标签交换路径。该方法还包括对存储在入口路由器中的至少一个虚拟路由和转发（VRF）表中的一个执行第一查找，由此第一查找从存储在入口路由器中的多个路由表中识别一个路由表，每个路由表与多个标签交换路径中的一个相关联，并且在一个路由表上执行第二查找，其中该路由表定义入口路由器与用于虚拟专用网（VPN）的出口路由器之间的关联标签交换路径，在第一个站点和第二个站点之间。

4. 发明授权

US07050940B2 Method and system for maintaining and examining timers for network connections 失效
标题翻译：用于维护和检查网络连接的定时器的方法和系统
公开(公告)号：US07050940B2
公开(公告)日：2006-05-23
申请号：US10802235
申请日：2004-03-17
申请人： Claude Basso , Richard J. Blasiak , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen , Natarajan Vaidhyanathan , Colin B. Verrilli
发明人： Claude Basso , Richard J. Blasiak , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen , Natarajan Vaidhyanathan , Colin B. Verrilli
IPC分类号： G06F15/00
CPC分类号： H04L69/28
摘要： System and method for maintenance and examination of timers for a computer system having connections in a networking system. Timer values in a connection table each indicate a timeout for a timer for a connection, where each connection has multiple timers, and one of the timer values is written to a global timer array for each connection such that the global timer array can be scanned to determine when timeouts occur for active connections. Sparse restart of a timer includes restarting the timer if data is communicated with a connected computer before the timeout occurs and after a predetermined time interval after timer start, and not restarting the timer if data is communicated before the timeout occurs and within the predetermined interval after timer start.
摘要翻译：用于维护和检查具有网络系统中的连接的计算机系统的定时器的系统和方法。连接表中的定时器值各自表示连接的定时器的超时，其中每个连接具有多个定时器，并且其中一个定时器值被写入到每个连接的全局定时器阵列，以便可以扫描全局定时器阵列确定活动连接的超时时间。定时器的稀疏重新启动包括重新启动定时器，如果数据在超时发生之前与连接的计算机通信，并且在定时器启动之后的预定时间间隔之后重新启动，并且如果在超时发生之前传输数据并且在超时之后的预定时间间隔内，则不重新启动定时器定时器启动。

5. 发明授权

US08726132B2 Checksum verification accelerator 失效
标题翻译：校验和验证加速器
公开(公告)号：US08726132B2
公开(公告)日：2014-05-13
申请号：US13302688
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H03M13/00
CPC分类号： H04L1/0079 , H04L1/0061 , H04L1/0072
摘要： Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
摘要翻译：公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。该系统利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。系统通过将数据包校验和与第二个校验和进行比较来验证数据包。

6. 发明授权

US08619782B2 Bidirectional packet flow transformation 失效
标题翻译：双向分组流转换
公开(公告)号：US08619782B2
公开(公告)日：2013-12-31
申请号：US13325624
申请日：2011-12-14
申请人： Claude Basso , Jean L Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean L Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/28 , H04L12/56 , G06F7/00 , G06F17/00
CPC分类号： H04L29/0653 , H04L45/50 , H04L47/2441
摘要： A network packet includes a packet key that includes one or more source-destination field pairs that each include a source field and a destination field. For each selected source-destination field pair, first and second sections are selected in the packet key. A source field value is extracted from the source field and a destination field value is extracted from the destination field. For each source bit of the source field value: a destination bit is selected from the destination field; an OR logic function is applied to the source bit and the destination bit to generate a first resulting value is stored at the same bit position as the source bit in the first section; an AND logic function is applied to the source bit and the destination bit to generate a second resulting value stored at the same bit position as the source bit in the second section.
摘要翻译：网络分组包括分组密钥，其包括一个或多个源 - 目的地字段对，每个源对目的字段对都包括源字段和目的地字段。对于每个选择的源 - 目的地字段对，在分组密钥中选择第一和第二部分。从源字段提取源字段值，并从目标字段提取目的字段值。对于源字段值的每个源位：从目标字段中选择目标位; 将OR逻辑功能应用于源位，并将目标位产生为第一结果值，存储在与第一段中的源位相同的位位置; 将AND逻辑功能应用于源位和目标位，以产生存储在与第二部分中的源位相同的位位置处的第二个结果值。

7. 发明申请

US20120218885A1 SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES 失效
标题翻译：基于分组属性选择接收队列
公开(公告)号：US20120218885A1
公开(公告)日：2012-08-30
申请号：US13466914
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/24
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法。网络处理器接收数据包流中的第一数据包和适于存储接收数据包的一组接收队列。网络处理器通过读取第一数据分组中的流标识来处理第一数据分组; 确定第一数据分组的服务质量; 将流标识和服务质量映射到用于选择用于路由第一数据分组的第一接收队列的索引; 以及利用所述索引将所述第一数据分组路由到所述第一接收队列。

8. 发明申请

US20120204190A1 Merging Result from a Parser in a Network Processor with Result from an External Coprocessor 失效
标题翻译：从具有外部协处理器结果的网络处理器中的解析器合并结果
公开(公告)号：US20120204190A1
公开(公告)日：2012-08-09
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.
摘要翻译：提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。使用一个附加队列来排列存储解析器结果的结果队列的地址。协处理器的结果是在简单的响应寄存器中接收的。协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

9. 发明申请

US20120192190A1 Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications 失效
标题翻译：用于处理端点和网络节点通信的主机以太网适配器
公开(公告)号：US20120192190A1
公开(公告)日：2012-07-26
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

10. 发明申请

US20120155267A1 SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES 审中-公开
标题翻译：基于分组属性选择接收队列
公开(公告)号：US20120155267A1
公开(公告)日：2012-06-21
申请号：US13302285
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/26
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method, a system, and a computer program product for operating a network processor. The network processor processing a received data packet by reading a flow identification in the data packet; determining a quality of service criteria (QoSC) for the data packet; mapping the flow identification and the QoSC into an index for selecting a receive-queue for routing the data packet; and utilizing the index to route the data packet to the receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法，系统和计算机程序产品。网络处理器通过读取数据分组中的流标识来处理接收到的数据分组; 确定数据包的服务质量标准（QoSC）; 将流标识和QoSC映射到用于选择用于路由数据分组的接收队列的索引; 并利用索引将数据包路由到接收队列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式