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1. 发明授权

US07050940B2 Method and system for maintaining and examining timers for network connections 失效
标题翻译：用于维护和检查网络连接的定时器的方法和系统
公开(公告)号：US07050940B2
公开(公告)日：2006-05-23
申请号：US10802235
申请日：2004-03-17
申请人： Claude Basso , Richard J. Blasiak , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen , Natarajan Vaidhyanathan , Colin B. Verrilli
发明人： Claude Basso , Richard J. Blasiak , Philippe Damon , Laurent Frelechoux , Brahmanand K. Gorti , Bernard Metzler , Bay V. Nguyen , Natarajan Vaidhyanathan , Colin B. Verrilli
IPC分类号： G06F15/00
CPC分类号： H04L69/28
摘要： System and method for maintenance and examination of timers for a computer system having connections in a networking system. Timer values in a connection table each indicate a timeout for a timer for a connection, where each connection has multiple timers, and one of the timer values is written to a global timer array for each connection such that the global timer array can be scanned to determine when timeouts occur for active connections. Sparse restart of a timer includes restarting the timer if data is communicated with a connected computer before the timeout occurs and after a predetermined time interval after timer start, and not restarting the timer if data is communicated before the timeout occurs and within the predetermined interval after timer start.
摘要翻译：用于维护和检查具有网络系统中的连接的计算机系统的定时器的系统和方法。连接表中的定时器值各自表示连接的定时器的超时，其中每个连接具有多个定时器，并且其中一个定时器值被写入到每个连接的全局定时器阵列，以便可以扫描全局定时器阵列确定活动连接的超时时间。定时器的稀疏重新启动包括重新启动定时器，如果数据在超时发生之前与连接的计算机通信，并且在定时器启动之后的预定时间间隔之后重新启动，并且如果在超时发生之前传输数据并且在超时之后的预定时间间隔内，则不重新启动定时器定时器启动。

2. 发明授权

US07283529B2 Method and system for supporting a dedicated label switched path for a virtual private network over a label switched communication network 有权
标题翻译：用于在标签交换通信网络上支持用于虚拟专用网络的专用标签交换路径的方法和系统
公开(公告)号：US07283529B2
公开(公告)日：2007-10-16
申请号：US10383973
申请日：2003-03-07
申请人： Claude Basso , Brahmanand K. Gorti , Natarajan Vaidhyanathan , Colin B. Verrilli
发明人： Claude Basso , Brahmanand K. Gorti , Natarajan Vaidhyanathan , Colin B. Verrilli
IPC分类号： H04L12/28 , H04L12/56 , G06F15/173
CPC分类号： H04L45/54 , H04L12/4641 , H04L45/50
摘要： A system and method for transmitting data from a first site to a second site over a shared Multi-Protocol Label Switched (MPLS) network comprising a plurality of routers, including an ingress router in communication with the first site and an egress router in communication with the second site, includes configuring a plurality of label switching paths between the ingress router and the egress router over a plurality of label switching devices. The method further includes performing a first lookup on one of at least one virtual routing and forwarding (VRF) table stored in the ingress router, whereby the first lookup identifies one routing table from a plurality of routing tables stored in the ingress router, each routing table being associated with one of the plurality of label switched paths, and performing a second lookup on the one routing table, wherein the routing table defines the associated label switched path between the ingress router and the egress router for a virtual private network (VPN) between the first site and the second site.
摘要翻译：一种用于通过共享的多协议标签交换（MPLS）网络从第一站点传送数据到第二站点的系统和方法，包括多个路由器，包括与第一站点通信的入口路由器和与第一站点通信的出口路由器第二站点包括通过多个标签交换设备在入口路由器和出口路由器之间配置多个标签交换路径。该方法还包括对存储在入口路由器中的至少一个虚拟路由和转发（VRF）表中的一个执行第一查找，由此第一查找从存储在入口路由器中的多个路由表中识别一个路由表，每个路由表与多个标签交换路径中的一个相关联，并且在一个路由表上执行第二查找，其中该路由表定义入口路由器与用于虚拟专用网（VPN）的出口路由器之间的关联标签交换路径，在第一个站点和第二个站点之间。

3. 发明申请

US20120204190A1 Merging Result from a Parser in a Network Processor with Result from an External Coprocessor 失效
标题翻译：从具有外部协处理器结果的网络处理器中的解析器合并结果
公开(公告)号：US20120204190A1
公开(公告)日：2012-08-09
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.
摘要翻译：提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。使用一个附加队列来排列存储解析器结果的结果队列的地址。协处理器的结果是在简单的响应寄存器中接收的。协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

4. 发明申请

US20120192190A1 Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications 失效
标题翻译：用于处理端点和网络节点通信的主机以太网适配器
公开(公告)号：US20120192190A1
公开(公告)日：2012-07-26
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

5. 发明授权

US07715428B2 Multicore communication processing 有权
标题翻译：多核通讯处理
公开(公告)号：US07715428B2
公开(公告)日：2010-05-11
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/66 , H04J3/16 , H04J3/22
CPC分类号： H04L47/50
摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了用于处理数据处理设备之间的通信的机制。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

6. 发明授权

US09088594B2 Providing to a parser and processors in a network processor access to an external coprocessor 有权
标题翻译：向网络处理器中的解析器和处理器提供对外部协处理器的访问
公开(公告)号：US09088594B2
公开(公告)日：2015-07-21
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/30 , H04L29/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

7. 发明申请

US20120204002A1 Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor 有权
标题翻译：提供给网络处理器中的解析器和处理器访问外部协处理器
公开(公告)号：US20120204002A1
公开(公告)日：2012-08-09
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

8. 发明申请

US20080181245A1 System and Method for Multicore Communication Processing 有权
标题翻译：多核通信处理系统与方法
公开(公告)号：US20080181245A1
公开(公告)日：2008-07-31
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L47/50
摘要： A system and method for multicore processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了一种用于数据处理设备之间的通信的多核处理的系统和方法。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

9. 发明授权

US08576864B2 Host ethernet adapter for handling both endpoint and network node communications 失效
标题翻译：主机以太网适配器，用于处理端点和网络节点通信
公开(公告)号：US08576864B2
公开(公告)日：2013-11-05
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28 , H04J1/16
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

10. 发明授权

US08468546B2 Merging result from a parser in a network processor with result from an external coprocessor 失效
公开(公告)号：US08468546B2
公开(公告)日：2013-06-18
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F3/00
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.

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