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1. 发明申请

US20050156234A1 Control of hot carrier injection in a metal-oxide semiconductor device 有权
标题翻译：在金属氧化物半导体器件中控制热载流子注入
公开(公告)号：US20050156234A1
公开(公告)日：2005-07-21
申请号：US10977732
申请日：2004-10-29
申请人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
发明人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
IPC分类号： H01L21/336 , H01L29/40 , H01L29/41 , H01L29/76 , H01L29/78 , H01L31/113
CPC分类号： H01L29/402 , H01L29/41 , H01L29/7835
摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.
摘要翻译：形成MOS器件，其包括第一导电类型的半导体层，以及形成在靠近半导体层的上表面的半导体层中的第二导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开。在靠近半导体层的上表面的半导体层中至少部分地在第一和第二源/漏区之间形成漂移区。绝缘层形成在半导体层的上表面的至少一部分上方和漂移区的至少一部分上方。栅极形成在绝缘层上并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在漂移区的至少一部分上方的绝缘层上的屏蔽结构。屏蔽结构被配置为使得MOS器件中的热载流子注入劣化量被控制为在漂移区域的上表面上的屏蔽结构的覆盖量的函数。

2. 发明申请

US20080003703A1 CONTROL OF HOT CARRIER INJECTION IN A METAL-OXIDE SEMICONDUCTOR DEVICE 有权
标题翻译：金属氧化物半导体器件中热载体注入的控制
公开(公告)号：US20080003703A1
公开(公告)日：2008-01-03
申请号：US11853417
申请日：2007-09-11
申请人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
发明人： Peter Gammel , Isik Kizilyalli , Marco Mastrapasqua , Muhammed Shibib , Zhijian Xie , Shuming Xu
IPC分类号： H01L21/66
CPC分类号： H01L29/402 , H01L29/41 , H01L29/7835
摘要： In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.
摘要翻译：在包括形成在靠近半导体层的上表面的第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域的金属氧化物半导体器件中，形成在靠近上部的半导体层中的漂移区域半导体层的表面，并且至少部分地在第一和第二源极/漏极区之间，形成在半导体层的上表面的至少一部分上的绝缘层和形成在绝缘层上的栅极，并且至少部分地在第一和/ 第一和第二源极/漏极区域，用于控制器件中热载流子注入劣化量的方法包括以下步骤：在绝缘层上形成屏蔽结构，该屏蔽结构位于漂移区域的至少一部分上方并且基本上在栅极和第二源极/漏极区域; 以及调整所述屏蔽结构在所述漂移区域的上表面上的覆盖范围，以便在保持所述器件中的击穿电压大于或等于规定值的同时使热载流子注入劣化的量最小化。

3. 发明申请

US20050110083A1 Metal-oxide-semiconductor device having improved gate arrangement 审中-公开
标题翻译：具有改进的栅极布置的金属氧化物半导体器件
公开(公告)号：US20050110083A1
公开(公告)日：2005-05-26
申请号：US10719197
申请日：2003-11-21
申请人： Peter Gammel , Muhammed Shibib , Zhijian Xie , Shuming Xu
发明人： Peter Gammel , Muhammed Shibib , Zhijian Xie , Shuming Xu
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/423 , H01L29/76
CPC分类号： H01L29/7801 , H01L21/823481 , H01L29/0619 , H01L29/0696 , H01L29/4238 , H01L29/7816 , H01L29/7835
摘要： An MOS device comprises a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced laterally apart relative to one another and are formed in an active region of the semiconductor layer. The MOS device further comprises a gate formed above the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The gate is configured such that a dimension of the gate, defined substantially parallel to at least one of the first and second source/drain regions, is confined to be substantially within the active region of the device. An isolation structure is formed in the semiconductor layer, the isolation structure being configured to substantially isolate the first source/drain region from the second source/drain region.
摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。第一和第二源极/漏极区域相对于彼此横向间隔开，并且形成在半导体层的有源区中。 MOS器件还包括形成在半导体层上方的接近半导体层的上表面并且至少部分地在第一和第二源极/漏极区之间的栅极。栅极被配置为使得基本上平行于第一和第二源极/漏极区域中的至少一个限定的栅极的尺寸被限制为基本上位于器件的有源区域内。在半导体层中形成隔离结构，隔离结构被配置为使第一源极/漏极区域与第二源极/漏极区域基本上隔离。

4. 发明授权

US08406159B2 Dual mode transceiver 有权
标题翻译：双模收发器
公开(公告)号：US08406159B2
公开(公告)日：2013-03-26
申请号：US13342898
申请日：2012-01-03
申请人： Darcy Poulin , Peter Gammel
发明人： Darcy Poulin , Peter Gammel
IPC分类号： H04J3/00
CPC分类号： H04B1/44 , H04B1/006 , H04L5/143 , H04L5/1469 , H04L27/0002 , H04L27/0008
摘要： A circuit is disclosed with an external coupling port for coupling to an external antenna, for example. The circuit has an FDD receive path including a narrowband passband filter. The circuit has a TDD receive path bypassing the narrowband passband filter but relying on a same amplifier. The circuit also has an FDD transmit path including a narrowband passband filter. The circuit has a TDD transmit path bypassing the narrowband passband filter of the FDD transmit path but relying on a same transmit amplifier. A switching configuration allows the circuit to operate in TDD mode, alternating between the TDD receive path and the TDD transmit path and in the FDD mode wherein the FDD transmit and receive paths are simultaneously coupled to the external coupling port.
摘要翻译：公开了一种用于耦合到外部天线的外部耦合端口的电路。电路具有包括窄带通带滤波器的FDD接收路径。电路具有绕过窄带通带滤波器但依赖于相同放大器的TDD接收路径。电路还具有包括窄带通带滤波器的FDD发送路径。该电路具有绕过FDD发射路径的窄带通带滤波器但依赖于相同发射放大器的TDD发射路径。切换配置允许电路在TDD模式下操作，在TDD接收路径和TDD发送路径之间交替，并且在FDD模式中，其中FDD发送和接收路径同时耦合到外部耦合端口。

5. 发明申请

US20070293115A1 Process for making an on-chip vacuum tube device 失效
标题翻译：制造片上真空管装置的方法
公开(公告)号：US20070293115A1
公开(公告)日：2007-12-20
申请号：US11649197
申请日：2007-01-03
申请人： Peter Gammel , Richard Howard , Omar Lopez , Wei Zhu
发明人： Peter Gammel , Richard Howard , Omar Lopez , Wei Zhu
IPC分类号： H01J9/00
CPC分类号： H01J23/165 , H01J9/02 , H01J9/022 , H01J21/105 , H01J25/00 , H01J2209/18
摘要： A microelectromechanical microwave vacuum tube device is disclosed. The device consists of a cathode formed on a substrate, the cathode comprising electron emitters. A cathode emission control grid is also attached to the device substrate. The device further includes an output structure where amplified microwave power is removed from the device. In the device, the cathode surface and the grid surface are substantially parallel to each other and substantially perpendicular to the substrate. One of either the cathode, the grid, or both the cathode and the grid, are attached to the device substrate by one or more flexural members. The device further comprises an anode that is substantially parallel to the cathode surface and the grid surface.
摘要翻译：公开了一种微机电微波真空管装置。该器件由形成在衬底上的阴极组成，阴极包括电子发射体。阴极发射控制栅格也附着到器件衬底。该装置还包括其中放大的微波功率从该装置移除的输出结构。在该器件中，阴极表面和栅格表面基本上彼此平行并基本垂直于衬底。阴极，栅格或阴极和栅格中的一个通过一个或多个弯曲构件附接到器件衬底。该装置还包括基本上平行于阴极表面和栅格表面的阳极。

6. 发明授权

US08089906B2 Dual mode transceiver 有权
标题翻译：双模收发器
公开(公告)号：US08089906B2
公开(公告)日：2012-01-03
申请号：US12367073
申请日：2009-02-06
申请人： Darcy Poulin , Peter Gammel
发明人： Darcy Poulin , Peter Gammel
IPC分类号： H04J3/00
CPC分类号： H04B1/44 , H04B1/006 , H04L5/143 , H04L5/1469 , H04L27/0002 , H04L27/0008
摘要： A circuit is disclosed with an external coupling port for coupling to an external antenna, for example. The circuit has an FDD receive path including a narrowband passband filter. The circuit has a TDD receive path bypassing the narrowband passband filter but relying on a same amplifier. The circuit also has an FDD transmit path including a narrowband passband filter. The circuit has a TDD transmit path bypassing the narrowband passband filter of the FDD transmit path but relying on a same transmit amplifier. A switching configuration allows the circuit to operate in TDD mode, alternating between the TDD receive path and the TDD transmit path and in the FDD mode wherein the FDD transmit and receive paths are simultaneously coupled to the external coupling port.
摘要翻译：公开了一种用于耦合到外部天线的外部耦合端口的电路。电路具有包括窄带通带滤波器的FDD接收路径。电路具有绕过窄带通带滤波器但依赖于相同放大器的TDD接收路径。电路还具有包括窄带通带滤波器的FDD发送路径。该电路具有绕过FDD发射路径的窄带通带滤波器但依赖于相同发射放大器的TDD发射路径。切换配置允许电路在TDD模式下操作，在TDD接收路径和TDD发送路径之间交替，并且在FDD模式中，其中FDD发送和接收路径同时耦合到外部耦合端口。

7. 发明申请

US20100202325A1 DUAL MODE TRANSCEIVER 有权
标题翻译：双模收发器
公开(公告)号：US20100202325A1
公开(公告)日：2010-08-12
申请号：US12367073
申请日：2009-02-06
申请人： Darcy POULIN , Peter Gammel
发明人： Darcy POULIN , Peter Gammel
IPC分类号： H04J4/00 , H04B1/44 , H04L5/14
CPC分类号： H04B1/44 , H04B1/006 , H04L5/143 , H04L5/1469 , H04L27/0002 , H04L27/0008
摘要： A circuit is disclosed with an external coupling port for coupling to an external antenna, for example. The circuit has an FDD receive path including a narrowband passband filter. The circuit has a TDD receive path bypassing the narrowband passband filter but relying on a same amplifier. The circuit also has an FDD transmit path including a narrowband passband filter. The circuit has a TDD transmit path bypassing the narrowband passband filter of the FDD transmit path but relying on a same transmit amplifier. A switching configuration allows the circuit to operate in TDD mode, alternating between the TDD receive path and the TDD transmit path and in the FDD mode wherein the FDD transmit and receive paths are simultaneously coupled to the external coupling port.
摘要翻译：公开了一种用于耦合到外部天线的外部耦合端口的电路。电路具有包括窄带通带滤波器的FDD接收路径。电路具有绕过窄带通带滤波器但依赖于相同放大器的TDD接收路径。电路还具有包括窄带通带滤波器的FDD发送路径。该电路具有绕过FDD发射路径的窄带通带滤波器但依赖于相同发射放大器的TDD发射路径。切换配置允许电路在TDD模式下操作，在TDD接收路径和TDD发送路径之间交替，并且在FDD模式中，其中FDD发送和接收路径同时耦合到外部耦合端口。

8. 发明申请

US20120171968A1 DUAL MODE TRANSCEIVER 有权
标题翻译：双模收发器
公开(公告)号：US20120171968A1
公开(公告)日：2012-07-05
申请号：US13342898
申请日：2012-01-03
申请人： Darcy Poulin , Peter Gammel
发明人： Darcy Poulin , Peter Gammel
IPC分类号： H04B1/44
CPC分类号： H04B1/44 , H04B1/006 , H04L5/143 , H04L5/1469 , H04L27/0002 , H04L27/0008
摘要： A circuit is disclosed with an external coupling port for coupling to an external antenna, for example. The circuit has an FDD receive path including a narrowband passband filter. The circuit has a TDD receive path bypassing the narrowband passband filter but relying on a same amplifier. The circuit also has an FDD transmit path including a narrowband passband filter. The circuit has a TDD transmit path bypassing the narrowband passband filter of the FDD transmit path but relying on a same transmit amplifier. A switching configuration allows the circuit to operate in TDD mode, alternating between the TDD receive path and the TDD transmit path and in the FDD mode wherein the FDD transmit and receive paths are simultaneously coupled to the external coupling port.
摘要翻译：公开了一种用于耦合到外部天线的外部耦合端口的电路。电路具有包括窄带通带滤波器的FDD接收路径。电路具有绕过窄带通带滤波器但依赖于相同放大器的TDD接收路径。电路还具有包括窄带通带滤波器的FDD发送路径。该电路具有绕过FDD发射路径的窄带通带滤波器但依赖于相同发射放大器的TDD发射路径。切换配置允许电路在TDD模式下操作，在TDD接收路径和TDD发送路径之间交替，并且在FDD模式中，其中FDD发送和接收路径同时耦合到外部耦合端口。

9. 发明申请

US20050287786A1 Device and method using isotopically enriched silicon 失效
标题翻译：使用同位素富集硅的装置和方法
公开(公告)号：US20050287786A1
公开(公告)日：2005-12-29
申请号：US10875029
申请日：2004-06-23
申请人： Peter Gammel , Bailey Jones , Isik Kizilyalli , Hugo Safar
发明人： Peter Gammel , Bailey Jones , Isik Kizilyalli , Hugo Safar
IPC分类号： H01L21/20 , H01L21/322 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L29/10 , H01L29/16 , H01L29/167 , H01L29/78
CPC分类号： H01L29/16 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/322 , H01L21/823412 , H01L21/823807 , H01L29/1033 , H01L29/167 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a process for manufacturing a semiconductor device that can be incorporated into an integrated circuit. The method includes, forming a first doped layer of isotopically enriched silicon over a foundational substrate, forming a second layer of an isotopically enriched semiconductor material silicon over the first doped layer, and constructing active devices on the second layer. The device includes a first doped layer of an isotopically enriched semiconductor material and a second layer of an isotopically enriched semiconductor material located over the first doped layer, and active devices located on the second layer.
摘要翻译：本发明提供一种可并入集成电路的半导体器件的制造方法。该方法包括：在基底衬底上形成同位素富集的硅的第一掺杂层，在第一掺杂层上形成同位素富集的半导体材料硅的第二层，以及在第二层上构建有源器件。该器件包括同位素富集的半导体材料的第一掺杂层和位于第一掺杂层上方的同位素富集的半导体材料的第二层以及位于第二层上的有源器件。

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