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1. 发明授权

US06661691B2 Interconnection structure and methods 失效
标题翻译：互连结构与方法
公开(公告)号：US06661691B2
公开(公告)日：2003-12-09
申请号：US10115763
申请日：2002-04-02
申请人： Peter Fricke , Andrew Koll , Andrew L. Van Brocklin , Daryl Anderson
发明人： Peter Fricke , Andrew Koll , Andrew L. Van Brocklin , Daryl Anderson
IPC分类号： G11C506
CPC分类号： G11C5/063 , H01L23/522 , H01L27/112 , H01L2924/0002 , Y10S977/789 , Y10S977/801 , Y10S977/906 , Y10S977/943 , H01L2924/00
摘要： Interconnection structures for integrated circuits have a first array of cells, at least a second array of cells parallel to the first array, and interconnections disposed for connecting cells of the first array with cells of the second array, at least some of the interconnections being disposed along axes oriented obliquely to the first and second arrays. First and second sets of oblique axes of interconnections may be parallel or opposed to each other. The interconnections may include obliquely slanted pillars or stair-stepped pillars disposed along the oblique axes. Methods for fabricating and using such structures are disclosed.
摘要翻译：用于集成电路的互连结构具有第一阵列阵列，平行于第一阵列的至少第二阵列阵列，以及布置用于将第一阵列的单元与第二阵列的单元相连接的互连，至少部分布线被布置沿着与第一和第二阵列倾斜定向的轴。互连的第一组和第二组倾斜轴线可以彼此平行或相对。互连可以包括倾斜的立柱或沿斜轴设置的阶梯式柱。公开了制造和使用这种结构的方法。

2. 发明授权

US06717215B2 Memory structures 失效
标题翻译：内存结构
公开(公告)号：US06717215B2
公开(公告)日：2004-04-06
申请号：US10177240
申请日：2001-06-21
申请人： Peter Fricke , Andrew L. Van Brocklin , Andrew Koll
发明人： Peter Fricke , Andrew L. Van Brocklin , Andrew Koll
IPC分类号： H01L2712
CPC分类号： H01L45/085 , H01L27/224 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/145 , H01L45/148 , H01L45/1633
摘要： A memory structure that includes a first electrode, a second electrode, a thermal conduction limiting electrode having a thermal conductivity that is less than a thermal conductivity of the first electrode, a memory storage elementdisposed between the thermal conduction limiting electrode and the second electrode, and a control element disposed between the second electrode and the first electrode.
摘要翻译：一种存储器结构，包括第一电极，第二电极，导热率小于第一电极的热导率的导热限制电极，布置在导热限制电极和第二电极之间的存储器存储元件，以及设置在所述第二电极和所述第一电极之间的控制元件。

3. 发明授权

US06842369B2 Intermesh memory device 失效
标题翻译： Intermesh内存设备
公开(公告)号：US06842369B2
公开(公告)日：2005-01-11
申请号：US10141609
申请日：2002-05-07
申请人： Andrew Koll , Peter Fricke , Andrew L. Van Brocklin
发明人： Andrew Koll , Peter Fricke , Andrew L. Van Brocklin
IPC分类号： G11C17/12 , G11C5/02 , G11C17/00 , H01L27/10 , G11C7/00
CPC分类号： G11C17/00 , G11C5/025
摘要： An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.
摘要翻译：互相间存储器件包括每个具有可确定电阻值的存储器组件和每个通过一个或多个存储器组件控制电流的电子开关，使得将电位施加到存储器组件。互连存储器件的第一电子开关电耦合到存储器组件的输入端，而第二电子开关电耦合到存储器组件的输出端。第一电子开关和第二电子开关被配置在一起以向存储器组件施加电位。

4. 发明授权

US06821848B2 Tunnel-junction structures and methods 失效
标题翻译：隧道结结构和方法
公开(公告)号：US06821848B2
公开(公告)日：2004-11-23
申请号：US10286157
申请日：2002-10-30
申请人： Dennis Lazaroff , Kenneth M. Kramer , James E. Ellenson , Neal W. Meyer , David Punsalan , Kurt Ulmer , Peter Fricke , Andrew Koll , Andrew L. Van Brocklin
发明人： Dennis Lazaroff , Kenneth M. Kramer , James E. Ellenson , Neal W. Meyer , David Punsalan , Kurt Ulmer , Peter Fricke , Andrew Koll , Andrew L. Van Brocklin
IPC分类号： H01L21336
CPC分类号： G11C13/003 , G11C17/16 , G11C17/18 , G11C2213/76
摘要： Tunnel-junction structures are fabricated by any of a set of related methods that form two or more tunnel junctions simultaneously. The fabrication methods disclosed are compatible with conventional CMOS fabrication practices, including both single damascene and dual damascene processes. The simultaneously formed tunnel junctions may have different areas. In some embodiments, tub-well structures are formed with sloped sidewalls. In some embodiments, an oxide-metal-oxide film stack on the sidewall of a tub-well is etched to form the tunnel junctions. Memory circuits, other integrated circuit structures, substrates carrying microelectronics, and other electronic devices made by the methods are disclosed.
摘要翻译：隧道结结构通过同时形成两个或更多个隧道结的一组相关方法中的任一种来制造。所公开的制造方法与常规CMOS制造实践兼容，包括单镶嵌和双镶嵌工艺。同时形成的隧道结可以具有不同的区域。在一些实施例中，浴盆结构形成有倾斜的侧壁。在一些实施例中，蚀刻在浴缸的侧壁上的氧化物 - 金属氧化物膜堆叠以形成隧道结。公开了存储电路，其它集成电路结构，携带微电子的衬底以及通过该方法制造的其它电子器件。

5. 发明授权

US06687147B2 Cubic memory array with diagonal select lines 失效
标题翻译：具有对角选择线的立方体存储器阵列
公开(公告)号：US06687147B2
公开(公告)日：2004-02-03
申请号：US10202174
申请日：2002-07-23
申请人： Peter Fricke , Andrew L. Van Brocklin , Andrew Koll
发明人： Peter Fricke , Andrew L. Van Brocklin , Andrew Koll
IPC分类号： G11C506
CPC分类号： H01L27/0688 , G11C5/025 , G11C7/18 , H01L21/8221 , H01L27/105 , H01L27/1052
摘要： A method of creating a memory circuit preferably includes (1) forming a first plurality of select-lines in a plane substantially parallel to a substrate, (2) forming a second plurality of select-lines in a plane substantially parallel to the substrate, where the second plurality of select-lines is divided into first and second groups, where the first group is formed in a direction normal to that of the first plurality of select-lines and the second group is formed in a direction substantially diagonal to that of the first group, (3) forming a plurality of pillars normal to the substrate, and (4) forming an array of memory cells, each memory cell being respectively coupled to a pillar and one of each of said first and second pluralities of select-lines.
摘要翻译：一种创建存储器电路的方法优选地包括：（1）在基本上平行于衬底的平面中形成第一组多个选择线，（2）在基本上平行于衬底的平面中形成第二组选择线，其中第二组选择线被分成第一组和第二组，其中第一组形成在与第一组多个选择线的方向垂直的方向上，并且第二组形成在与第一组大致对角线的方向上第一组，（3）形成与衬底垂直的多个支柱，以及（4）形成存储器单元的阵列，每个存储单元分别耦合到一个柱和每个所述第一和第二多个选择线中的一个。

6. 发明授权

US06940085B2 Memory structures 失效
标题翻译：内存结构
公开(公告)号：US06940085B2
公开(公告)日：2005-09-06
申请号：US10115744
申请日：2002-04-02
申请人： Peter Fricke , Andrew Koll , Dennis M. Lazaroff , Andrew L. Van Brocklin
发明人： Peter Fricke , Andrew Koll , Dennis M. Lazaroff , Andrew L. Van Brocklin
IPC分类号： H01L27/10 , H01L27/105 , H01L47/00 , H01L29/00
CPC分类号： H01L27/224 , H01L27/101 , H01L27/2409 , H01L27/2481 , H01L45/06 , H01L45/1226 , H01L45/1233
摘要： A memory structure that includes a first electrode, a second electrode, a third electrode, a control element disposed between the first electrode and the second electrode, and a memory storage element disposed between the second electrode and the third electrode. At least one of the control element and memory storage element is protected from contamination by at least one of the first electrode, second electrode and third electrode.
摘要翻译：一种存储器结构，包括第一电极，第二电极，第三电极，设置在第一电极和第二电极之间的控制元件，以及设置在第二电极和第三电极之间的存储器存储元件。控制元件和存储器存储元件中的至少一个被保护以免受第一电极，第二电极和第三电极中的至少一个的污染。

7. 发明授权

US06707087B2 Structure of chalcogenide memory element 有权
标题翻译：硫族化物记忆元件的结构
公开(公告)号：US06707087B2
公开(公告)日：2004-03-16
申请号：US10177239
申请日：2002-06-21
申请人： Peter Fricke , Andrew Koll , Andrew L. Van Brocklin
发明人： Peter Fricke , Andrew Koll , Andrew L. Van Brocklin
IPC分类号： H01L27108
CPC分类号： G11C13/0004 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/148
摘要： A memory structure that includes a control element electrode, a heater electrode, a memory element electrode, a chalcogenide based memory element disposed between the memory element electrode and the heater electrode, and a control element disposed between the heater electrode and the control element electrode.
摘要翻译：一种存储结构，其包括控制元件电极，加热器电极，存储元件电极，设置在存储元件电极和加热器电极之间的基于硫族化物的存储元件，以及设置在加热器电极和控制元件电极之间的控制元件。

8. 发明授权

US06781858B2 Cubic memory array 有权
标题翻译：立方体内存阵列
公开(公告)号：US06781858B2
公开(公告)日：2004-08-24
申请号：US10650895
申请日：2003-08-29
申请人： Peter Fricke , Andrew L. Van Brocklin , Daryl Anderson
发明人： Peter Fricke , Andrew L. Van Brocklin , Daryl Anderson
IPC分类号： G11C502
CPC分类号： H01L21/8221 , G11C5/025 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/2409 , H01L27/2418 , H01L27/249 , H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.
摘要翻译：在具有平坦表面的基板上制造立方体存储器阵列。立方体存储器阵列包括多个第一选择线，其组织在平行于平面的多个平面中。多个第二选择线形成在垂直于基板的平面的柱上。多个存储单元分别耦合到多个第一和第二选择线。

9. 发明授权

US06643159B2 Cubic memory array 失效
标题翻译：立方体内存阵列
公开(公告)号：US06643159B2
公开(公告)日：2003-11-04
申请号：US10116213
申请日：2002-04-02
申请人： Peter Fricke , Andrew L. Van Brocklin , Daryl Anderson
发明人： Peter Fricke , Andrew L. Van Brocklin , Daryl Anderson
IPC分类号： G11C502
CPC分类号： H01L21/8221 , G11C5/025 , H01L27/0688 , H01L27/105 , H01L27/1052 , H01L27/2409 , H01L27/2418 , H01L27/249 , H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/148
摘要： A cubic memory array is fabricated on a substrate having a planar surface. The cubic memory array includes a plurality of first select-lines organized in more than one plane parallel to the planar surface. A plurality of second select-lines is formed in pillars disposed orthogonal to the planer surface of the substrate. A plurality of memory cells are respectively coupled to the plurality of first and plurality of second select-lines.
摘要翻译：在具有平坦表面的基板上制造立方体存储器阵列。立方体存储器阵列包括多个第一选择线，其组织在平行于平面的多个平面中。多个第二选择线形成在垂直于基板的平面的柱上。多个存储单元分别耦合到多个第一和第二选择线。

10. 发明授权

US06570795B1 Defective memory component of a memory device used to represent a data bit in a bit sequence 有权
标题翻译：用于表示位序列中的数据位的存储器件的存储器组件有缺陷
公开(公告)号：US06570795B1
公开(公告)日：2003-05-27
申请号：US10120473
申请日：2002-04-10
申请人： Peter Fricke , Andrew L. Van Brocklin , Daryl Anderson
发明人： Peter Fricke , Andrew L. Van Brocklin , Daryl Anderson
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C17/00 , G11C17/06 , G11C17/16
摘要： A memory device includes memory components that represent a logic value corresponding to a data bit in a bit sequence. A defective memory component in the memory device represents a data bit in the bit sequence. An additional memory component in the memory device represents an encode bit in the bit sequence, where the encode bit indicates whether the bit sequence is inverted.
摘要翻译：存储器件包括表示与位序列中的数据位对应的逻辑值的存储器组件。存储器件中的缺陷存储器部件表示位序列中的数据位。存储器件中的附加存储器组件表示位序列中的编码位，其中编码位指示位序列是否被反转。

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