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1. 发明授权

US6098125A Method of mapping fibre channel frames based on control and type header fields 失效
标题翻译：基于控制和类型头字段映射光纤通道帧的方法
公开(公告)号：US6098125A
公开(公告)日：2000-08-01
申请号：US71276
申请日：1998-05-01
申请人： Peter Fiacco , Bradley Roach , Karl M. Henson
发明人： Peter Fiacco , Bradley Roach , Karl M. Henson
IPC分类号： G06F13/14 , H04L12/56 , G06F13/00
CPC分类号： H04L47/6215 , H04L47/2441 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9042 , H04L49/9047
摘要： A method and apparatus for processing and transferring frames of data in a computer data link that maps incoming frames to a specific buffer ring in host memory based on routing control and type fields in each frame. More particularly, a Fibre Channel link port contains receiver routing code (RRCode) registers that allow host software to set up routing control (R.sub.-- CTL) match and mask fields, and TYPE match and mask fields. The link port uses these registers to match and mask against corresponding R.sub.-- CTL/TYPE fields in a received frame to determine which of several R.sub.-- CTL/TYPE host memory buffer rings should be used to store the received frame. The link port places a code (RRCode) in a start of frame (SOF) status word associated with a frame. The RRCode indicates a specific R.sub.-- CTL/TYPE host memory buffer ring, or indicates that no match was found or that multiple matches were found. A protocol engine reads the RRCode field in the SOF status word of the received frame, and queues a direct memory access (DMA) operation to an appropriate R.sub.-- CTL/TYPE buffer ring. The host may then process the contents of the indicated buffer ring. Since the buffer rings are "pre-sorted" as to frame type, the host may more efficiently respond to incoming frames.
摘要翻译：一种在计算机数据链路中处理和传送数据帧的方法和装置，该计算机数据链路基于每个帧中的路由控制和类型字段将输入帧映射到主机存储器中的特定缓冲环。更具体地，光纤通道链路端口包含允许主机软件建立路由控制（R-CTL）匹配和掩码字段以及TYPE匹配和掩码字段的接收机路由代码（RRCode）寄存器。链路端口使用这些寄存器来匹配和掩蔽接收到的帧中的相应的R-CTL / TYPE字段，以确定应该使用几个R-CTL / TYPE主机内存缓冲区中的哪一个来存储接收到的帧。链路端口将代码（RRCode）放置在与帧相关联的帧（SOF）状态字的起始处。 RRCode指示特定的R-CTL / TYPE主机内存缓冲区环，或表示未找到匹配或找到多个匹配。协议引擎读取接收到的帧的SOF状态字中的RRCode字段，并将直接存储器访问（DMA）操作排队到适当的R-CTL / TYPE缓冲环。然后，主机可以处理指示的缓冲环的内容。由于缓冲环针对帧类型进行“预排序”，所以主机可以更有效地响应输入帧。

2. 发明授权

US06728861B1 Queuing fibre channel receive frames 有权
标题翻译：排队光纤通道接收帧
公开(公告)号：US06728861B1
公开(公告)日：2004-04-27
申请号：US10382728
申请日：2003-03-04
申请人： Bradley Roach , Raul Oteyza , Karl M. Henson
发明人： Bradley Roach , Raul Oteyza , Karl M. Henson
IPC分类号： G06F1206
CPC分类号： H04L47/50
摘要： A frame receive queue may perform disassembly and validation operations on frames received by a node in a Fiber Channel network. The frame receive queue may store information used for later processing of the frames, e.g., header data and the first eight payload words, in an on-chip memory for fast processor access. The payload data for the frames may be stored in a larger, external memory.
摘要翻译：帧接收队列可以对由光纤通道网络中的节点接收的帧执行反汇编和验证操作。帧接收队列可以存储用于稍后处理帧的信息，例如头部数据和前八个有效载荷字，用于快速处理器访问。帧的有效载荷数据可以存储在较大的外部存储器中。

3. 发明授权

US6005849A Full-duplex communication processor which can be used for fibre channel frames 失效
标题翻译：全双工通信处理器，可用于光纤通道帧
公开(公告)号：US6005849A
公开(公告)日：1999-12-21
申请号：US937066
申请日：1997-09-24
申请人： Bradley Roach , Peter Fiacco , Greg Scherer
发明人： Bradley Roach , Peter Fiacco , Greg Scherer
IPC分类号： G06F13/10 , G06F13/12 , H04L12/28 , H04L12/56 , H04L29/06 , H04L29/10 , H04B1/56 , H04L5/14
CPC分类号： H04L49/901 , G06F13/124 , H04L12/2801 , H04L29/06 , H04L49/90 , H04L49/9089 , H04L69/12
摘要： A full duplex communication processor simultaneously sends and receives frames of data and commands. Separate transmit and receive protocol engines are controlled by separate sequencers. This enables frames of data to be received and transmitted simultaneously without involving a host CPU on a frame-by-frame basis.
摘要翻译：全双工通信处理器同时发送和接收数据帧和数据帧。单独的发送和接收协议引擎由独立的定序器控制。这使得数据帧能够同时接收和传输，而不需要逐帧地涉及主机CPU。

4. 发明授权

US06829660B2 Supercharge message exchanger 有权
标题翻译：增压消息交换机
公开(公告)号：US06829660B2
公开(公告)日：2004-12-07
申请号：US10316604
申请日：2002-12-10
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F1328
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
摘要翻译：具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。第二RAM还被配置为存储来自至少两个引擎的I / O完成。当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。第一个处理器处理存储在第一个RAM中的I / O完成。第二处理器处理存储在第二RAM中的I / O完成。

5. 发明授权

US06304910B1 Communication processor having buffer list modifier control bits 失效
标题翻译：具有缓冲器列表修改器控制位的通信处理器
公开(公告)号：US06304910B1
公开(公告)日：2001-10-16
申请号：US08937065
申请日：1997-09-24
申请人： Bradley Roach , Peter Fiacco , Greg Scherer , Stuart Berman , David Duckman
发明人： Bradley Roach , Peter Fiacco , Greg Scherer , Stuart Berman , David Duckman
IPC分类号： G06F1300
CPC分类号： H04L49/9089 , H04L29/06 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9052 , H04L49/9094 , H04L69/12
摘要： A communication processor sends and receives frames of data and commands. Transmit and receive protocol engine is controlled by host driver software which utilizes predetermined bits to indicate which frame is the last frame in a series of frames. This information is then placed in the transmit frame before it is sent.
摘要翻译：通信处理器发送和接收数据帧和数据帧。发送和接收协议引擎由主机驱动程序软件控制，主机驱动程序使用预定位来指示哪一帧是一系列帧中的最后一帧。然后将该信息发送到发送帧之前。

6. 发明授权

US07363396B2 Supercharge message exchanger 有权
标题翻译：增压消息交换机
公开(公告)号：US07363396B2
公开(公告)日：2008-04-22
申请号：US11361344
申请日：2006-02-24
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F13/12 , G06F3/00 , G06F13/28
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
摘要翻译：具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。第二RAM还被配置为存储来自至少两个引擎的I / O完成。当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。第一个处理器处理存储在第一个RAM中的I / O完成。第二处理器处理存储在第二RAM中的I / O完成。

7. 发明授权

US07096296B2 Supercharge message exchanger 失效
公开(公告)号：US07096296B2
公开(公告)日：2006-08-22
申请号：US10995456
申请日：2004-11-22
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F13/24 , G06F13/32
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

8. 发明申请

US20060143341A1 Supercharge message exchanger 有权
公开(公告)号：US20060143341A1
公开(公告)日：2006-06-29
申请号：US11361344
申请日：2006-02-24
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F13/38
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

9. 发明申请

US20050097240A1 Supercharge message exchanger 失效
标题翻译：增压消息交换机
公开(公告)号：US20050097240A1
公开(公告)日：2005-05-05
申请号：US10995456
申请日：2004-11-22
申请人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
发明人： Michael Liu , Bradley Roach , Sam Su , Peter Fiacco
IPC分类号： G06F13/12 , G06F13/14 , G06F13/28
CPC分类号： G06F13/28 , G06F13/387
摘要： A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.
摘要翻译：具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。第二RAM还被配置为存储来自至少两个引擎的I / O完成。当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。第一个处理器处理存储在第一个RAM中的I / O完成。第二处理器处理存储在第二RAM中的I / O完成。

10. 发明授权

US07159048B2 Direct memory access (DMA) transfer buffer processor 有权
标题翻译：直接存储器访问（DMA）传输缓冲处理器
公开(公告)号：US07159048B2
公开(公告)日：2007-01-02
申请号：US10179816
申请日：2002-06-24
申请人： Bradley Roach , David Duckman , Eric Peel , Qing Xue
发明人： Bradley Roach , David Duckman , Eric Peel , Qing Xue
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.
摘要翻译： DMA（直接存储器访问）交换块（DXB）处理器可以包括用于通过总线将数据从本地存储器写入主机存储器的接收处理器，例如外围部件互连扩展（PCI / X）总线和传输处理器，用于将通过总线从主机存储器检索的数据写入本地存储器。每个处理器可以包括高优先级队列和正常优先级队列。控制程序生成DXB，每个DXB包括由控制程序分配的标签和对应于直接存储器访问操作的存储器描述符。存储器描述符可以包括主机存储器描述符（地址/长度）和一个或多个本地存储器描述符。控制程序将DXB写入高速缓存行溢出操作中的一个队列。传送处理器可以包括两个通道寄存器，使处理器能够同时执行两个PCI / X数据传输。

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