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1. 发明申请

US20050070083A1 Wafer-level moat structures 有权
标题翻译：晶圆级护城河结构
公开(公告)号：US20050070083A1
公开(公告)日：2005-03-31
申请号：US10672165
申请日：2003-09-26
申请人： Michael Johnson , Peter Elenius , Deok Kim
发明人： Michael Johnson , Peter Elenius , Deok Kim
IPC分类号： H01L20060101 , H01L21/44 , H01L21/60 , H01L21/66 , H01L23/31 , H01L23/485
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05567 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
摘要翻译：晶片级CSP（200）包括来自晶片的至少一个管芯（202）。晶片级CSP具有多个焊球垫（206），每个焊球垫处的焊球（308）和围绕每个焊球的聚合物环（310）。在晶片级CSP的制造期间，在设置在晶片上的聚合物层（412）的表面中形成护城河（204）。当晶片被加热到焊球的回流温度时，从聚合物套环的临时液化残余物（502）从聚合物套环流出。护城河充当材料流动的障碍，限制了液化时残留物扩散的距离。来自聚合物套环的残余物保留在由护城河限定的区域（314）内。全深的护城河（312）完全延伸穿过聚合物层。或者，部分深度护城河（712和912）部分地延伸穿过聚合物层。提交摘要的理解是，根据37 C.F.R.不会将其用于解释或限制权利要求的范围或含义。 §1.72（b）。

2. 发明申请

US20050069782A1 Forming partial-depth features in polymer film 有权
标题翻译：在聚合物膜中形成部分深度特征
公开(公告)号：US20050069782A1
公开(公告)日：2005-03-31
申请号：US10672201
申请日：2003-09-26
申请人： Peter Elenius , Michael Johnson
发明人： Peter Elenius , Michael Johnson
IPC分类号： G03C5/00 , G03F20060101 , G03F1/14 , G03F9/00 , G21K5/00
CPC分类号： G03F1/50
摘要： A photomask (1900) for producing partial-depth features (712 and 912) in a photo-imageable polymer layer (412) on a wafer of a chip scale package (200) using exposure tools capable of resolving sizes of a critical dimension or larger, has a plurality of chrome lines (2101-2103). Each chrome line has a width (2105) that is less than the critical dimension, and each chrome line of the plurality of chrome lines is spaced apart less than the critical dimension. The plurality of chrome lines produces a single partial-depth feature, such as a via, through part of a thickness of the polymer layer. Alternatively, the photomask has a plurality of chrome circles (2206), each chrome circle having a diameter less than the critical dimension and being spaced apart less than the critical dimension, which produces the partial-depth feature. The photomask may also have chrome of width greater than the critical dimension and spaced from other chrome by a distance greater than the critical dimension, which produces a full-depth feature through the entire thickness of the polymer film. The partial-depth feature and the full-depth feature are produced substantially simultaneously during a single series of photo-imaging steps. By preselecting a size, shape and distance between the chrome, the photomask is capable of inscribing discernable markings on the polymer layer, of changing the thickness of the polymer layer, and of changing an optical property of the surface of the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
摘要翻译：一种光掩模（1900），用于使用能够分辨关键尺寸或更大尺寸的曝光工具在芯片级封装（200）的晶片上的可光成像聚合物层（412）中产生部分深度特征（712和912）具有多条铬线（2101-2103）。每个铬线具有小于临界尺寸的宽度（2105），并且多个铬线的每个铬线间隔开小于临界尺寸。多条铬线通过聚合物层的厚度的一部分产生单一部分深度特征，例如通孔。或者，光掩模具有多个铬圆（2206），每个铬圆的直径小于临界尺寸，并且间隔开小于临界尺寸，产生部分深度特征。光掩模还可以具有大于临界尺寸的宽度的铬，并且与其它铬隔开大于临界尺寸的距离，其通过聚合物膜的整个厚度产生全深度特征。部分深度特征和全深度特征在单个系列的光成像步骤期间基本上同时产生。通过预先选择铬之间的尺寸，形状和距离，光掩模能够在聚合物层上刻划可辨别的标记，改变聚合物层的厚度和改变聚合物层的表面的光学性质。提交摘要的理解是，根据37 C.F.R.不会将其用于解释或限制权利要求的范围或含义。 §1.72（b）。

3. 发明授权

US08487437B2 Electronic device package and method for fabricating the same 有权
标题翻译：电子器件封装及其制造方法
公开(公告)号：US08487437B2
公开(公告)日：2013-07-16
申请号：US12885233
申请日：2010-09-17
申请人： Peter Elenius , Deok Hoon Kim , Young Sang Cho
发明人： Peter Elenius , Deok Hoon Kim , Young Sang Cho
IPC分类号： H01L23/48
CPC分类号： H01L23/10 , H01L23/3128 , H01L23/564 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L27/14618 , H01L27/14621 , H01L27/14627 , H01L27/14683 , H01L31/0203 , H01L2224/13 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13147 , H01L2224/14155 , H01L2224/16237 , H01L2224/16503 , H01L2224/29011 , H01L2224/29014 , H01L2224/29035 , H01L2224/29109 , H01L2224/29111 , H01L2224/29113 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32 , H01L2224/32227 , H01L2224/32503 , H01L2224/73203 , H01L2224/73204 , H01L2224/81191 , H01L2224/81447 , H01L2224/8181 , H01L2224/8182 , H01L2224/83 , H01L2224/83102 , H01L2224/83191 , H01L2224/83447 , H01L2224/8381 , H01L2224/83825 , H01L2224/9211 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01077 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/15321 , H01L2924/15788 , H01L2224/81 , H01L2924/00014 , H01L2224/73103 , H01L2924/00012 , H01L2924/00
摘要： An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device.
摘要翻译：电子器件封装包括衬底组件，设置为面对衬底组件的电子器件，以及密封环或环，其包括设置在衬底组件和电子器件之间的密封层和接合层，其中密封环 s）具有围绕电子器件的密封区域的闭环形状，并且通过密封层和密封层焊盘与熔点低于熔点的低熔点材料层的反应形成接合层密封层和密封环垫。接合层由密封层，密封环垫和低熔点材料的金属间化合物形成，其熔点高于低熔点材料的熔融温度。器件封装还包括在衬底组件和电子器件之间的接合形式的电连接。

4. 发明授权

US07057292B1 Solder bar for high power flip chips 有权
标题翻译：焊接棒用于大功率倒装芯片
公开(公告)号：US07057292B1
公开(公告)日：2006-06-06
申请号：US09575298
申请日：2000-05-19
申请人： Peter Elenius , Hong Yang
发明人： Peter Elenius , Hong Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5386 , H01L21/4853 , H01L23/49816 , H01L23/49838 , H01L2224/0401 , H01L2224/05552 , H01L2224/13012 , H01L2224/14051 , H01L2924/01322 , H01L2924/01327 , H01L2924/10253 , H05K3/341 , H05K3/3436 , H01L2924/00 , H01L2924/00012
摘要： A solder bar compatible with conventional flip chip technology fabrication methods for high power/high current applications includes first and second generally circular solder pads of diameter D formed upon a substrate and connected by a solder bar pad of width BW. The centers of the generally circular solder pads are spaced apart by distance BL (bar length). A mass of solder having volume VB is formed over the first and second generally circular solder pads and over the solder bar pad to form a dog-bone shaped solder bar. The solder bar reaches height H1 above the centers of the first and second generally circular solder pads, and reaching height H2 above the midpoint of the solder bar pad. The values for diameter D, bar length BL, bar width BW, and solder volume VB are selected in such manner that H1 and H2 are approximately equal. Conventional circular (as viewed from above) solder bumps can be formed upon the same substrate; in this case, heights H1 and H2 are made approximately equal to the height of the conventional solder bumps.
摘要翻译：与用于高功率/高电流应用的常规倒装芯片技术制造方法兼容的焊料棒包括直径为D的第一和第二通常为圆形的焊盘，其形成在基板上并且通过宽度为BW的焊条焊盘连接。大致圆形焊盘的中心间隔距离BL（条长度）。具有体积VB的焊料块形成在第一和第二大致圆形的焊盘之上并且在焊料条焊盘上形成，以形成狗骨形焊料条。焊料棒在第一和第二大致圆形焊盘的中心之上达到高度H 1，并且在焊料条焊盘的中点之上达到高度H 2。以H 1和H 2近似相等的方式选择直径D，条长度BL，条宽BW和焊料体积VB的值。常规的圆形（如上所述）可以在相同的基板上形成焊料凸块; 在这种情况下，H 1和H 2的高度大致等于常规焊料凸块的高度。

5. 发明授权

US06287893B1 Method for forming chip scale package 失效
标题翻译：芯片级封装形成方法
公开(公告)号：US06287893B1
公开(公告)日：2001-09-11
申请号：US09114204
申请日：1998-07-13
申请人： Peter Elenius , Harry Hollack
发明人： Peter Elenius , Harry Hollack
IPC分类号： H01L2144
CPC分类号： H01L24/12 , G06F1/1601 , G06F2200/1612 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05647 , H01L2224/10 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01051 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
摘要翻译：用于倒装芯片集成电路的芯片级封装设计包括在半导体晶片的上表面上的再分布金属层，用于同时形成焊料凸块焊盘以及将这种焊料凸块焊盘与导电接合焊盘电连接的金属再分布迹线底层集成电路。将图案化的钝化层施加在再分布金属层上。相对较大的延性焊球被放置在焊料凸块焊盘上，用于将芯片级封装安装到电路板或其它基板上，而不需要底部填充材料。半导体晶片的背面可以通过在处理期间的机械强度的涂层来保护。还公开了在晶片处理级别形成这种芯片级封装的方法。

6. 发明授权

US08141245B2 Method of forming a circuit board with improved via design 失效
标题翻译：用改进的通孔设计形成电路板的方法
公开(公告)号：US08141245B2
公开(公告)日：2012-03-27
申请号：US12344643
申请日：2008-12-29
申请人： Kevin C. Olson , Alan E. Wang , Peter Elenius , Thomas W. Goodman
发明人： Kevin C. Olson , Alan E. Wang , Peter Elenius , Thomas W. Goodman
IPC分类号： H01K3/10
CPC分类号： H05K3/44 , H05K1/056 , H05K3/002 , H05K3/0052 , H05K3/4641 , H05K3/4644 , H05K2201/0166 , H05K2201/0909 , H05K2201/0919 , H05K2201/09554 , H05K2203/135 , Y10T29/49126 , Y10T29/49156 , Y10T29/49167 , Y10T428/12361 , Y10T428/24322
摘要： A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.
摘要翻译：多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖导电片的边缘。绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。

7. 发明授权

US07126164B2 Wafer-level moat structures 有权
标题翻译：晶圆级护城河结构
公开(公告)号：US07126164B2
公开(公告)日：2006-10-24
申请号：US10672165
申请日：2003-09-26
申请人： Michael E. Johnson , Peter Elenius , Deok Hoon Kim
发明人： Michael E. Johnson , Peter Elenius , Deok Hoon Kim
IPC分类号： H01L33/00
CPC分类号： H01L24/13 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05567 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/13007 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A wafer-level CSP (200) includes at least one die (202) from a wafer. The wafer-level CSP has a plurality of solder ball pads (206), a solder ball (308) at each solder ball pad and a polymer collar (310) around each solder ball. A moat (204) is formed in the surface of a polymer layer (412) disposed on the wafer during manufacturing of the wafer-level CSP. A temporarily liquified residual (502) from the polymer collar, which occurs while the wafer is heated to the reflow temperature of the solder ball, flows from the polymer collar. The moat acts as a barrier to material flow, limiting the distance that the residual spreads while liquified. The residual from the polymer collar remains within a region (314) defined by the moat. A full-depth moat (312) extends completely through the polymer layer. Alternatively, a partial-depth moat (712 and 912) extends partially through the polymer layer. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims pursuant to 37 C.F.R. §1.72(b).
摘要翻译：晶片级CSP（200）包括来自晶片的至少一个管芯（202）。晶片级CSP具有多个焊球垫（206），每个焊球垫处的焊球（308）和围绕每个焊球的聚合物环（310）。在晶片级CSP的制造期间，在设置在晶片上的聚合物层（412）的表面中形成护城河（204）。当晶片被加热到焊球的回流温度时，从聚合物套环的临时液化残余物（502）从聚合物套环流出。护城河充当材料流动的障碍，限制了液化时残留物扩散的距离。来自聚合物套环的残余物保留在由护城河限定的区域（314）内。全深的护城河（312）完全延伸穿过聚合物层。或者，部分深度护城河（712和912）部分地延伸穿过聚合物层。提交摘要的理解是，根据37 C.F.R.不会将其用于解释或限制权利要求的范围或含义。 §1.72（b）。

8. 发明授权

US06750135B2 Method for forming chip scale package 失效
标题翻译：芯片级封装形成方法
公开(公告)号：US06750135B2
公开(公告)日：2004-06-15
申请号：US09885846
申请日：2001-06-20
申请人： Peter Elenius , Harry Hollack
发明人： Peter Elenius , Harry Hollack
IPC分类号： H01L2144
CPC分类号： H01L24/12 , G06F1/1601 , G06F2200/1612 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05647 , H01L2224/10 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/01051 , H01L2924/01057 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/351 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.
摘要翻译：用于倒装芯片集成电路的芯片级封装设计包括在半导体晶片的上表面上的再分布金属层，用于同时形成焊料凸块焊盘以及将这种焊料凸块焊盘与导电接合焊盘电连接的金属再分布迹线底层集成电路。将图案化的钝化层施加在再分布金属层上。相对较大的延性焊球被放置在焊料凸块焊盘上，用于将芯片级封装安装到电路板或其它基板上，而不需要底部填充材料。半导体晶片的背面可以通过在处理期间的机械强度的涂层来保护。还公开了在晶片处理级别形成这种芯片级封装的方法。

9. 发明申请

US20050124196A1 Single or multi-layer printed circuit board with improved via design 失效
标题翻译：具有改进的通孔设计的单层或多层印刷电路板
公开(公告)号：US20050124196A1
公开(公告)日：2005-06-09
申请号：US10987480
申请日：2004-11-11
申请人： Kevin Olson , Alan Wang , Peter Elenius , Thomas Goodman
发明人： Kevin Olson , Alan Wang , Peter Elenius , Thomas Goodman
IPC分类号： H05K1/05 , H05K1/02 , H05K3/00 , H05K3/44 , H05K3/46 , H01R13/15
CPC分类号： H05K3/002 , H05K1/056 , H05K3/0052 , H05K3/403 , H05K3/44 , H05K3/445 , H05K3/4623 , H05K3/4641 , H05K3/4644 , H05K2201/0166 , H05K2201/0397 , H05K2201/0909 , H05K2201/09181 , H05K2201/0919 , H05K2201/09309 , H05K2201/09536 , H05K2201/09545 , H05K2201/09554 , H05K2201/09645 , H05K2201/09827 , H05K2203/1105 , H05K2203/135
摘要： A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.
摘要翻译：多层电路板的电路板或每个电路板包括涂覆有覆盖导电片的一个表面的绝缘顶层的导电片，覆盖导电片的另一表面的绝缘底层和覆盖导电片的边缘。绝缘中间层可以夹在多层电路板组件的一对相邻电路板之间。无地通孔或通孔可以延伸通过一个或多个电路板，用于连接其相对表面上的电导体。

10. 发明授权

US06578755B1 Polymer collar for solder bumps 有权
标题翻译：用于焊锡凸块的聚合物套圈
公开(公告)号：US06578755B1
公开(公告)日：2003-06-17
申请号：US09668450
申请日：2000-09-22
申请人： Peter Elenius , Deok-Hoon Kim
发明人： Peter Elenius , Deok-Hoon Kim
IPC分类号： B23K3102
CPC分类号： B23K3/0623 , H01L21/4853 , H01L23/49816 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/10126 , H01L2224/11334 , H01L2224/13099 , H01L2224/13565 , H01L2224/16225 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01043 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H05K3/3436 , H05K2201/10977 , Y02P70/613 , H01L2924/00 , H01L2224/05599
摘要： A method of forming a polymer support ring, or collar, around the base of solder balls used to form solder joints includes forming patterned regions of uncured polymer material over each of the conductive solder bump pads on an IC package or other substrate to which the solder balls are to be attached. Preferably, the uncured polymer material is a no-flow underfill material that fluxes the solder bump pads. Pre-formed solder balls are then placed into the uncured polymer material onto their respective solder bump pads. A subsequent heating cycle raises the assembly to the reflow temperature of the solder balls, thereby attaching the solder balls to the underlying solder bump pads, and at least partially curing the polymer material to form a support collar at the base region of each attached solder ball.
摘要翻译：在用于形成焊接接头的焊料球的基部周围形成聚合物支撑环或环的方法包括在IC封装或其它衬底上的每个导电焊料凸块上形成未固化聚合物材料的图案化区域，焊料要附上球。优选地，未固化的聚合物材料是助焊剂焊盘的无流动底部填充材料。然后将预先形成的焊球放入未固化的聚合物材料到它们各自的焊料凸块上。随后的加热循环将组装升高到焊球的回流温度，从而将焊球附接到下面的焊料凸块焊盘，并且至少部分地固化聚合物材料，以在每个附着的焊球的基部区域形成支撑环。

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