专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07253091B2 Process for assembling three-dimensional systems on a chip and structure thus obtained 有权
标题翻译：用于组装如此获得的芯片和结构上的三维系统的方法
公开(公告)号：US07253091B2
公开(公告)日：2007-08-07
申请号：US10256336
申请日：2002-09-26
申请人： Peter D. Brewer , Michael G. Case , Andrew T. Hunter , Mehran Matloubian , John A. Roth , Carl W. Pobanz
发明人： Peter D. Brewer , Michael G. Case , Andrew T. Hunter , Mehran Matloubian , John A. Roth , Carl W. Pobanz
IPC分类号： H01L21/4763 , H01L23/34
CPC分类号： H01L24/95 , H01L21/6835 , H01L21/8221 , H01L21/8258 , H01L24/24 , H01L24/82 , H01L25/50 , H01L27/0605 , H01L27/0688 , H01L2221/68345 , H01L2221/6835 , H01L2224/24145 , H01L2224/95085 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/04953 , H01L2924/09701 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13064 , H01L2924/14 , H01L2924/1423 , H01L2924/3011 , Y10S438/928 , H01L2924/00
摘要： A method for assembling an electronic system with a plurality of layers. Recesses in formed in one or more dielectric layers and electronic components are positioned within the recesses. One or more layers containing the components are placed on a host substrate containing host circuits. Electrical interconnects are provided between and among the electronic components in the dielectric layers and the host circuits. The layers containing the components may also be provided by growing the electronic devices on a growth substrate. The growth substrate is then removed after the layer is attached to the host substrate.
摘要翻译：一种用于组装具有多层的电子系统的方法。在一个或多个电介质层和电子元件中形成的凹陷定位在凹槽内。将含有这些组分的一个或多个层放置在包含主体电路的主机衬底上。在电介质层和主电路中的电子部件之间提供电互连。包含组分的层也可以通过在生长衬底上生长电子器件来提供。然后在该层附着于该主体底物之后移除该生长衬底。

2. 发明授权

US5528209A Monolithic microwave integrated circuit and method 失效
标题翻译：单片微波集成电路及方法
公开(公告)号：US5528209A
公开(公告)日：1996-06-18
申请号：US430067
申请日：1995-04-27
申请人： Perry A. Macdonald , Lawrence E. Larson , Michael G. Case , Mehran Matloubian , Mary Y. Chen , David B. Rensch
发明人： Perry A. Macdonald , Lawrence E. Larson , Michael G. Case , Mehran Matloubian , Mary Y. Chen , David B. Rensch
IPC分类号： H01L21/822 , H01L27/04 , H01L27/06 , H01L29/205 , H01P3/08 , H03F3/54 , H03H7/38 , H01P5/00
CPC分类号： H01L27/0605 , H01L2223/6627 , H01L2223/6644 , H01L2223/6683
摘要： A monolithic microwave integrated circuit is formed by positioning a distributed, transmission-line network over a microwave-device structure. The ground plane of the transmission-line network adjoins an interconnect system of the microwave-device structure and signal lines of the transmission-line network are adapted to communicate with the microwave-device structure through orifices of the ground plane. The invention facilitates the use of low-cost silicon-based transistors in monolithic microwave integrated circuits.
摘要翻译：通过在微波器件结构上定位分布式传输线网络来形成单片微波集成电路。传输线网络的接地平面与微波器件结构的互连系统相邻，并且传输线网络的信号线适于通过接地平面的孔与微波器件结构通信。本发明有助于在单片微波集成电路中使用低成本硅基晶体管。

3. 发明授权

US5557140A Process tolerant, high-voltage, bi-level capacitance varactor diode 失效
标题翻译：工艺容差，高电压双电容变容二极管
公开(公告)号：US5557140A
公开(公告)日：1996-09-17
申请号：US420959
申请日：1995-04-12
申请人： Chanh M. Nguyen , Michael G. Case , William W. Hooper , Authi A. Narayanan
发明人： Chanh M. Nguyen , Michael G. Case , William W. Hooper , Authi A. Narayanan
IPC分类号： H01L29/93
CPC分类号： H01L29/93
摘要： A doping profile is disclosed for realizing a varactor diode that exhibits a high breakdown voltage V.sub.BR, e.g.,>100 volts, and a capacitance which has a bi-level characteristic. In particular, the capacitance has a C.sub.max level and a C.sub.min level. The doping profile includes two lightly doped regions and, between them, a third region with higher doping. The doping concentrations and widths of the first two regions substantially set the tuning ratio of C.sub.max /C.sub.min, and the doping concentration and width of the third region substantially sets the transition voltage V.sub.TR between the bi-level capacitances.
摘要翻译：公开了一种用于实现表现出高击穿电压VBR（例如> 100伏特）和具有双电平特性的电容的变容二极管的掺杂分布。特别地，电容具有Cmax电平和Cmin电平。掺杂分布包括两个轻掺杂区域，并且在它们之间具有较高掺杂的第三区域。前两个区域的掺杂浓度和宽度基本上设定了Cmax / Cmin的调谐比，并且第三区域的掺杂浓度和宽度基本上设定了双电平电容之间的转变电压VTR。

4. 发明授权

US5789994A Differential nonlinear transmission line circuit 失效
标题翻译：差分非线性传输线路电路
公开(公告)号：US5789994A
公开(公告)日：1998-08-04
申请号：US797542
申请日：1997-02-07
申请人： Michael G. Case , Gopal Raghavan
发明人： Michael G. Case , Gopal Raghavan
IPC分类号： H03K5/159 , H01P5/00
CPC分类号： H03K5/159
摘要： A differential nonlinear transmission line (NLTL) circuit has anti-parallel diode pairs along a balanced transmission line to generate well defined high-speed pulses with sharp positive and negative transitions from a time varying input signal. The input signal may carry an arbitrary DC bias voltage component that is suitable for digital logic circuits, such as current mode logic (CML) employing differential inputs.
摘要翻译：差分非线性传输线（NLTL）电路沿着平衡传输线具有反并联二极管对，以从时变输入信号产生具有清晰正和负转换的良好定义的高速脉冲。输入信号可以携带适合数字逻辑电路的任意DC偏置电压分量，例如采用差分输入的电流模式逻辑（CML）。

5. 发明授权

US06750709B2 Bipolar transistor-based linearizer with programmable gain and phase response system 失效
标题翻译：具有可编程增益和相位响应系统的双极晶体管线性化
公开(公告)号：US06750709B2
公开(公告)日：2004-06-15
申请号：US10021423
申请日：2001-11-30
申请人： Gopal Raghavan , Michael G. Case , Carl Pobanz
发明人： Gopal Raghavan , Michael G. Case , Carl Pobanz
IPC分类号： H03F126
CPC分类号： H03F3/58 , H03F1/3223 , H03F3/211
摘要： A bipolar transistor-based linearizer with programmable gain and phase response apparatus uses a splitter to separate an incoming RF signal into two equal components: in-phase (I) and quadrature (Q, ninety degrees delayed). The I signal then passes through a first bipolar variable gain amplifier (VGA) while the Q signal passes through a second bipolar VGA. After passing through the first and second VGAs, the amplified signals are combined at the output using a summer to produce a predistorted signal that drives a TWTA. The gains of each VGA are controlled using an RF power detector in conjunction with a bipolar gain/phase slope controller. Each gain can be adjusted separately to product a large range of linearization characteristics.
摘要翻译：具有可编程增益和相位响应装置的基于双极晶体管的线性化电路使用分离器将输入的RF信号分成两个相等的分量：同相（I）和正交（Q，九十度延迟）。然后，I信号通过第一双极可变增益放大器（VGA），同时Q信号通过第二个双极VGA。经过第一和第二VGA后，放大的信号在输出端使用一个加法器组合，以产生一个驱动TWTA的预失真信号。每个VGA的增益都使用RF功率检测器和双极增益/相位斜率控制器进行控制。每个增益可以单独调整，以产生大范围的线性化特性。

6. 发明授权

US5606195A High-voltage bipolar transistor utilizing field-terminated bond-pad electrodes 失效
标题翻译：采用场效应端接的焊盘电极的高电压双极晶体管
公开(公告)号：US5606195A
公开(公告)日：1997-02-25
申请号：US578796
申请日：1995-12-26
申请人： William W. Hooper , Michael G. Case , Chanh N. Nguyen
发明人： William W. Hooper , Michael G. Case , Chanh N. Nguyen
IPC分类号： H01L29/73 , H01L21/331 , H01L23/485 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/737 , H01L29/44 , H01L29/52
CPC分类号： H01L29/402 , H01L24/02 , H01L29/41708 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01078 , H01L2924/05042 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/14 , H01L2924/30105 , H01L2924/3025
摘要： A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.
摘要翻译：一种高压双极晶体管及其制造方法，其包括位于接合焊盘和下层半导体材料之间的屏蔽电极（或场 - 终端电极）。屏蔽电极夹在两个隔离电介质层之间。施加到接合焊盘的高电压在接合焊盘和屏蔽电极之间建立电场），防止场下渗入下面的半导体材料和反转。使用这种重叠的场效应结构，在晶体管中保持低漏电流和高击穿电压。当前重叠的场终端结构在接合焊盘之下提供了有效的场终止，并且由于其重叠设计，提供了更紧凑的晶体管。

7. 发明授权

US06288579B1 Method to increase frequency of digital circuits 失效
标题翻译：增加数字电路频率的方法
公开(公告)号：US06288579B1
公开(公告)日：2001-09-11
申请号：US09456099
申请日：1999-12-07
申请人： Gopal Raghavan , Michael G. Case
发明人： Gopal Raghavan , Michael G. Case
IPC分类号： H03K300
CPC分类号： H01P5/02
摘要： A method to design and fabricate circuits is disclosed which will permit such circuits to operate at higher frequencies. The method is particularly adapted to integrated digital circuits, and to differential sections of such circuits, but may be applied more broadly. A load on the output of an amplifying section of the circuit is designed employing a section of high impedance inductive transmission line nearest the output node, which is then connected to a section of low impedance capacitive transmission line, and then is terminated into a resistor which provides the 0 Hz load for the circuit. By reducing the effect of the resistor portion of the load, the capacitive transmission line section permits the entire load, as seen at the output of the amplifying section, to appear more ideally inductive than has previously been achieved. Due to this inductive appearance, response times are improved and the circuit is able to operate at significantly higher frequencies.
摘要翻译：公开了一种设计和制造电路的方法，其允许这种电路在较高频率下工作。该方法特别适用于集成数字电路，以及这些电路的差分部分，但可以更广泛地应用。电路放大部分的输出端的负载被设计为使用最接近输出节点的高阻抗感应传输线路，然后将其连接到低阻抗电容传输线路的一部分，然后终止于电阻器为电路提供0 Hz负载。通过减小负载的电阻部分的影响，电容传输线部分允许在放大部分的输出处看到的整个负载看起来比以前已经实现的更理想地感应。由于这种感应外观，响应时间得到改善，并且电路能够以显着更高的频率工作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式