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1. 发明申请

US20120272119A1 ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效
标题翻译：高速总线上的错误纠正代码保护的静态位通信
公开(公告)号：US20120272119A1
公开(公告)日：2012-10-25
申请号：US13535574
申请日：2012-06-28
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/05 , G06F11/10 , H03M13/29
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

2. 发明授权

US08234540B2 Error correcting code protected quasi-static bit communication on a high-speed bus 失效
标题翻译：在高速总线上纠错代码保护的准静态位通信
公开(公告)号：US08234540B2
公开(公告)日：2012-07-31
申请号：US12165788
申请日：2008-07-01
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

3. 发明申请

US20100005365A1 ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效
标题翻译：高速总线上的错误纠正代码保护的静态位通信
公开(公告)号：US20100005365A1
公开(公告)日：2010-01-07
申请号：US12165788
申请日：2008-07-01
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/09
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

4. 发明授权

US08516338B2 Error correcting code protected quasi-static bit communication on a high-speed bus 失效
标题翻译：在高速总线上纠错代码保护的准静态位通信
公开(公告)号：US08516338B2
公开(公告)日：2013-08-20
申请号：US13535574
申请日：2012-06-28
申请人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
发明人： Peter Buchmann , Kevin C. Gower , Robert J. Reese , Martin L. Schmatz , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： H03M13/13 , G06F11/10
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译：提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。

5. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

6. 发明申请

US20100005281A1 POWER-ON INITIALIZATION AND TEST FOR A CASCADE INTERCONNECT MEMORY SYSTEM 失效
标题翻译：串联互连存储器系统的上电初始化和测试
公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

7. 发明申请

US20090094476A1 DERIVING CLOCKS IN A MEMORY SYSTEM 失效
标题翻译：在记忆系统中传送时钟
公开(公告)号：US20090094476A1
公开(公告)日：2009-04-09
申请号：US12332396
申请日：2008-12-11
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00 , G06F1/06
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。该方法包括在集线器设备处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

8. 发明授权

US07478259B2 System, method and storage medium for deriving clocks in a memory system 失效
标题翻译：用于在存储器系统中导出时钟的系统，方法和存储介质
公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：一种用于在存储器系统中导出时钟的系统，方法和存储介质。该方法包括在集线器装置处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

9. 发明申请

US20100005214A1 ENHANCING BUS EFFICIENCY IN A MEMORY SYSTEM 审中-公开
标题翻译：在存储系统中提高总线效率
公开(公告)号：US20100005214A1
公开(公告)日：2010-01-07
申请号：US12165814
申请日：2008-07-01
申请人： Michael R. Trombley , Kevin C. Gower , Warren E. Maule
发明人： Michael R. Trombley , Kevin C. Gower , Warren E. Maule
IPC分类号： G06F13/42 , G06F13/36
CPC分类号： G06F13/405 , G06F13/4243 , G06F13/4256 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for enhancing bus efficiency and utilization in a memory system. The communication interface device includes a first bus interface to communicate on a high-speed bus, a second bus interface to communicate on a lower-speed bus, and clock ratio logic configurable to support multiple clock ratios between the high-speed bus and the lower-speed bus. The clock ratio logic reduces a high-speed clock frequency received at the first bus interface and outputs a reduced ratio of the high-speed clock frequency on the lower-speed bus via the second bus interface supporting variable frame sizes.
摘要翻译：一种用于提高存储系统中总线效率和利用率的通信接口设备，系统，方法和设计结构。通信接口设备包括用于在高速总线上通信的第一总线接口，用于在低速总线上进行通信的第二总线接口以及可配置为支持高速总线与低速总线之间的多个时钟比的时钟比率逻辑高速公交车时钟比率逻辑降低了在第一总线接口处接收的高速时钟频率，并且经由支持可变帧大小的第二总线接口输出低速总线上的高速时钟频率的减小的比率。

10. 发明授权

US08245105B2 Cascade interconnect memory system with enhanced reliability 有权
标题翻译：级联互连存储器系统具有增强的可靠性
公开(公告)号：US08245105B2
公开(公告)日：2012-08-14
申请号：US12166235
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
发明人： Timothy J. Dell , Kevin C. Gower , Warren E. Maule , Michael R. Trombley
IPC分类号： H03M13/00
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0781 , G06F11/1004 , G11C5/04 , G11C29/70 , G11C2029/0409 , G11C2029/0411
摘要： A hub device, memory system, and method for providing a cascade interconnect memory system with enhanced reliability. The hub device includes an interface to a high-speed bus for communicating with a memory controller. The memory controller and the hub device are included in a cascade interconnect memory system and the high-speed bus includes bit lanes and one or more clock lanes. The hub device also includes a bi-directional fault signal line in communication with the memory controller and readable by a service interface. The hub device also includes a fault isolation register (FIR) for storing information about failures detected at the hub device, the information including severity levels of the detected failures. In addition, the hub device includes error recovery logic for responding to a failure detected at the hub device.
摘要翻译：一种用于提供具有增强的可靠性的级联互连存储器系统的集线器设备，存储器系统和方法。集线器设备包括与高速总线的接口，用于与存储器控制器进行通信。存储器控制器和集线器设备包括在级联互连存储器系统中，并且高速总线包括位通道和一个或多个时钟通道。集线器设备还包括与存储器控制器通信并可由服务接口读取的双向故障信号线。集线器设备还包括用于存储关于在集线器设备处检测到的故障的信息的故障隔离寄存器（FIR），该信息包括检测到的故障的严重性级别。此外，集线器设备包括用于响应在集线器设备处检测到的故障的错误恢复逻辑。

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