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1. 发明授权

US5235592A Dynamic switch protocols on a shared medium network 失效
标题翻译：一个共享媒体网络的动态切换协议
公开(公告)号：US5235592A
公开(公告)日：1993-08-10
申请号：US744153
申请日：1991-08-13
申请人： Ting D. Cheng , Peter A. Franaszek , Christos J. Georgiou , Gregory M. Nordstrom , Thomas K. Philips , Martin W. Sachs , Anujan M. Varma , Thomas M. Walker
发明人： Ting D. Cheng , Peter A. Franaszek , Christos J. Georgiou , Gregory M. Nordstrom , Thomas K. Philips , Martin W. Sachs , Anujan M. Varma , Thomas M. Walker
IPC分类号： H04L12/417 , H04L29/06
CPC分类号： H04L29/06 , H04L12/417
摘要： Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume. The use of circuit switched protocols within a token bus protocol allows more general transmission sequences and improves the utilization of token bus bandwidth.

2. 发明授权

US4929940A Collision crossbar switch 失效
标题翻译：碰撞横梁开关
公开(公告)号：US4929940A
公开(公告)日：1990-05-29
申请号：US275164
申请日：1988-11-18
申请人： Peter A. Franaszek , Christos J. Georgiou
发明人： Peter A. Franaszek , Christos J. Georgiou
IPC分类号： H04Q3/52 , H04Q11/04
CPC分类号： H04L49/101 , H04L49/252 , H04Q11/04
摘要： A high speed collision N.times.M tri-state crossbar switch having M collision busses uses contention detection at the destination. In the event of a collision of messages, remedial action can be taken such as rerouting colliding messages over an alternate path provided by a second interconnection network with contention resolution capability. Collision detection codes are transmitted prior to the transmission of messages to each input port. The tri-state output buses are monitored for the collison detection codes to detect an error. In order to prevent damage to driver transistors connected to the tri-state buses when a contention occurs, current limiting is provided to limit the current through the driver transistors to a predetermined level.

3. 发明授权

US5345228A Very large scale modular switch 失效
标题翻译：非常大规模的模块化开关
公开(公告)号：US5345228A
公开(公告)日：1994-09-06
申请号：US785730
申请日：1991-10-31
申请人： Peter A. Franaszek , Christos J. Georgiou
发明人： Peter A. Franaszek , Christos J. Georgiou
IPC分类号： H04Q3/52 , G06F15/173 , H04Q11/04 , H04Q1/00
CPC分类号： H04Q11/0407
摘要： Switch resources for a one-sided crosspoint switch with distributed control (i.e., switch ports, internal busses and controllers) have been organized so that modular growth is facilitated by: (1) assigning each switch port uniquely to one of the controllers; (2) making each controller handle only the crosspoints connected to the switch ports assigned to it; (3) assigning each internal bus uniquely to one of the controllers; and (4) providing a network for the controllers to communicate with each other.
摘要翻译：已经组织了具有分布式控制（即，交换机端口，内部总线和控制器）的单向交叉点交换机的资源切换，以便通过以下方式促进模块化增长：（1）将每个交换机端口唯一地分配给控制器之一; （2）使每个控制器仅处理连接到分配给它的交换机端口的交叉点; （3）将每条内部总线唯一地分配给其中一个控制器; 和（4）提供用于控制器相互通信的网络。

4. 发明授权

US4952930A Multipath hierarchical network 失效
标题翻译：多路径分层网络
公开(公告)号：US4952930A
公开(公告)日：1990-08-28
申请号：US274101
申请日：1988-11-18
申请人： Peter A. Franaszek , Christos J. Georgiou
发明人： Peter A. Franaszek , Christos J. Georgiou
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： G06F15/17393 , H04L49/253 , H04L49/101 , H04L49/1515 , H04L49/25 , H04L49/254
摘要： A hierarchy of multipath networks selectively provides connections between a plurality of sources and a plurality of destinations in a communications system. The hierarchy comprises a first multipath network without buffering which consists of two or more stages and constituting a fast path for connecting a source to a destination. At least a second multipath network with buffering and comprising a plurality of stages constitutes an alternate, slower path for connecting a source to a destination in the event that a connection between the source and the destination is blocked in the fast path. The address field of a message from a source is examined at each stage to select an appropriate connection to the next stage and, if the connection is available, the message, stripped of the address field, is propagated to the second stage, but if the next stage is blocked, the message is stopped and a negative acknowledgment is returned to the source. Retransmission of the message through the second network of the hierarchy is initiated upon the receipt of a negative acknowledgment at the source. The concept may be extended to multiple levels, with only the last stage providing buffering.

5. 发明授权

US07574524B2 Method and system for on-demand allocation of a dynamic network of services 失效
标题翻译：动态服务网络按需分配的方法和系统
公开(公告)号：US07574524B2
公开(公告)日：2009-08-11
申请号：US10674962
申请日：2003-09-30
申请人： David F. Bantz , David M. Chess , Christos J. Georgiou , Jeffrey O. Kephart , Clifford A. Pickover
发明人： David F. Bantz , David M. Chess , Christos J. Georgiou , Jeffrey O. Kephart , Clifford A. Pickover
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L67/1008 , H04L67/1002 , H04L67/1029
摘要： A system and method for providing real-time, dynamic switching between first and second service providers each capable of providing a service for users over a communications network. The method includes steps of: establishing switching criterion for deciding when to switch service provision between the first service provider and second service provider; maintaining state information associated with a user's use of the service provided by a first service provider; switching between the first and second service provided over the communications network based on satisfaction of the switching criterion; and, migrating any state information maintained up to the time of switching to the second service. Preferably, the dynamic switching occurs in a manner substantially transparent to the user.
摘要翻译：一种用于在第一和第二服务提供商之间提供实时动态切换的系统和方法，每个服务提供商能够通过通信网络为用户提供服务。该方法包括以下步骤：建立用于决定何时切换第一服务提供商和第二服务提供商之间的服务提供的切换标准; 维护与用户对由第一服务提供商提供的服务的使用相关联的状态信息; 基于切换标准的满足，在通信网络上提供的第一和第二服务之间切换; 并且将维护的任何状态信息迁移到切换到第二服务的时间。优选地，动态切换以对用户基本透明的方式发生。

6. 发明授权

US5550860A Digital phase alignment and integrated multichannel transceiver employing same 失效
标题翻译：采用数字相位校准和集成多通道收发器
公开(公告)号：US5550860A
公开(公告)日：1996-08-27
申请号：US420102
申请日：1995-04-11
申请人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
发明人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
IPC分类号： H03M9/00 , H04L7/033 , H04L25/34
CPC分类号： H04L7/0338 , H03M9/00 , H04L7/005
摘要： A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.
摘要翻译：提供信号平滑和滤波功能以及滑动周期补偿的同步器和相位对准方法，并且允许多通道数字相位对准，总线偏移校正，在单个半导体芯片内集成多个收发器等。延迟线产生多个的输入信号的延迟输入副本。时钟相位调节器从参考时钟信号产生采样时钟信号。采样时钟信号可以被相位调整以偏离输入信号。经过一定的平滑和滤波功能后，选择逻辑检测采样时钟信号和输入副本之间的相位关系，并识别紧密同步的信号进行输出。使用该识别的复制信号，打滑周期补偿和重新定时逻辑输出与参考时钟信号同步的补偿数据输出信号。此外，提出了使用相位对准技术制造的集成多收发器。

7. 发明授权

US5535213A Ring configurator for system interconnection using fully covered rings 失效
标题翻译：环形配置器，用于使用全覆盖环的系统互连
公开(公告)号：US5535213A
公开(公告)日：1996-07-09
申请号：US355862
申请日：1994-12-14
申请人： Shien-Tai Pan , Ting Cheng , Christos J. Georgiou , George W. Nation , Chung-Sheng Li
发明人： Shien-Tai Pan , Ting Cheng , Christos J. Georgiou , George W. Nation , Chung-Sheng Li
IPC分类号： H04L12/46 , H04L12/56 , H04J15/00
CPC分类号： H04L45/02 , H04L12/4637
摘要： A ring configurator for interconnection of data processing and communication systems uses fully covered rings. The ring configuration mechanism can be used to construct a set of covering rings preserving full connectivity for system interconnect. The mechanism can also be used for establishing the routing table for each interconnected system during the system initialization time. To generate a set of edge-disjoint rings, a rotational mechanism is used. The rings are considered stretching along a horizontal direction with nodes aligned in columns across all the rings. With a proper relabeling of the nodes, nodes appearing in the same column position of each ring can be obtained by a simple rotation of the nodes from the previous column of the rings. Once the rotational position is determined for each column, a set of N-1 edge-disjoint rings can be constructed. To find an extra ring so that when combined with the N-1 rings thus found the ring constraints are satisfied, a node reduction technique is invoked. The procedure can be repeated until a set of N edge-disjoint rings satisfying the constraints are found.
摘要翻译：用于数据处理和通信系统互连的环形配置器使用完全覆盖的环。环配置机制可用于构建一套保护系统互连的完整连接的覆盖环。该机制还可用于在系统初始化时间期间为每个互连系统建立路由表。为了产生一组边缘不相交的环，使用旋转机构。这些环被认为沿水平方向伸展，节点对齐在所有环上。通过对节点的适当重新标定，出现在每个环的相同列位置的节点可以通过从前一列的环的简单旋转获得。一旦为每列确定了旋转位置，就可以构造一组N-1个不相交的环。为了找到一个额外的环，使得当与N-1环组合时，因此发现环约束被满足，节点减少技术被调用。可以重复该过程，直到找到满足约束的一组N个边缘不相交的环。

8. 发明授权

US5533072A Digital phase alignment and integrated multichannel transceiver employing same 失效
公开(公告)号：US5533072A
公开(公告)日：1996-07-02
申请号：US152108
申请日：1993-11-12
申请人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
发明人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
IPC分类号： H03M9/00 , H04L7/033 , H03D3/24
CPC分类号： H04L7/0338 , H03M9/00 , H04L7/005
摘要： A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

9. 发明授权

US5189314A Variable chip-clocking mechanism 失效
标题翻译：可变芯片时钟机制
公开(公告)号：US5189314A
公开(公告)日：1993-02-23
申请号：US754795
申请日：1991-09-04
申请人： Christos J. Georgiou , Thor A. Larsen , Eugen Schenfeld
发明人： Christos J. Georgiou , Thor A. Larsen , Eugen Schenfeld
IPC分类号： G06F15/78 , G06F1/04 , G06F1/08 , G06F1/20
CPC分类号： G06F1/206 , G06F1/08
摘要： The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.
摘要翻译：通过以更高的时钟速率运行内部电路，可以增加一些芯片（例如，VLSI处理器）的性能，但是使用更高的时钟速率受到芯片封装的散热能力的限制。描述了用于估计任何给定时间的耗散的累积热量的装置和方法。对于芯片空闲的时间，降低时钟速率以减少发热。芯片空闲时节省的热量可以稍后使用，将时钟频率提高到正常值以上，只要所产生的总热量不超过封装的散热能力即可。

10. 发明授权

US4845704A Switching system for integrated voice/data communications 失效
标题翻译：用于集成语音/数据通信的交换系统
公开(公告)号：US4845704A
公开(公告)日：1989-07-04
申请号：US33437
申请日：1987-04-01
申请人： Christos J. Georgiou , Gerald Lebizay
发明人： Christos J. Georgiou , Gerald Lebizay
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04Q11/04
摘要： A method of integrating the switching of voice and data between terminals connected to switch adapters. The switching of voice (or more generally synchronous signals) is accomplished by grouping voice samples in a first adapter and bound for the same destination or second adapter into a frame. Connections are then established between the two adapters and the frame is transmitted therethrough. A duplex method can also be set up by transmitting in both directions at the same time once a dual connection between the first and second adapter is established. Hence, a second group of voice samples bound for the first adapter is also formed ina frame. The two frames are then transmitted simultaneously in opposite directions through a dual connection in the switching matrix. Data is switched by storing data in respective memories of respective adapters, wherein each respective memory corresponds to a particular adapter to which the data stored therein is to be sent.

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