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1. 发明授权

US5189314A Variable chip-clocking mechanism 失效
标题翻译：可变芯片时钟机制
公开(公告)号：US5189314A
公开(公告)日：1993-02-23
申请号：US754795
申请日：1991-09-04
申请人： Christos J. Georgiou , Thor A. Larsen , Eugen Schenfeld
发明人： Christos J. Georgiou , Thor A. Larsen , Eugen Schenfeld
IPC分类号： G06F15/78 , G06F1/04 , G06F1/08 , G06F1/20
CPC分类号： G06F1/206 , G06F1/08
摘要： The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.
摘要翻译：通过以更高的时钟速率运行内部电路，可以增加一些芯片（例如，VLSI处理器）的性能，但是使用更高的时钟速率受到芯片封装的散热能力的限制。描述了用于估计任何给定时间的耗散的累积热量的装置和方法。对于芯片空闲的时间，降低时钟速率以减少发热。芯片空闲时节省的热量可以稍后使用，将时钟频率提高到正常值以上，只要所产生的总热量不超过封装的散热能力即可。

2. 发明授权

US5243334A Partitioned switch with distributed clocks 失效
标题翻译：分配开关分配时钟
公开(公告)号：US5243334A
公开(公告)日：1993-09-07
申请号：US752813
申请日：1991-08-30
申请人： Christos J. Georgiou , Thor A. Larsen
发明人： Christos J. Georgiou , Thor A. Larsen
IPC分类号： H04L12/64 , H04Q11/04
CPC分类号： H04Q11/04
摘要： A partitioned switch having distributed clocks includes a global matrix switch and one or more self-contained mini-switches. The mini-switches each contain ports connected via a local matrix switch. Communication between ports located in the same mini-switch is performed synchronously and in parallel via the local matrix switch. Communication between ports located in different mini-switches is performed asynchronously and serially via the global matrix switch. The mini-switches control the global matrix switch by serially and asynchronously sending control information to the global matrix switch.
摘要翻译：具有分布式时钟的分区交换机包括全局矩阵开关和一个或多个独立的微型开关。微型开关各自包含通过本地矩阵开关连接的端口。位于同一个微型开关中的端口之间的通信通过本地矩阵开关同步并行。位于不同小型交换机的端口之间的通信通过全局矩阵开关异步和串行地执行。微型开关通过串行和异步地将控制信息发送到全局矩阵开关来控制全局矩阵切换。

3. 发明授权

US5550860A Digital phase alignment and integrated multichannel transceiver employing same 失效
标题翻译：采用数字相位校准和集成多通道收发器
公开(公告)号：US5550860A
公开(公告)日：1996-08-27
申请号：US420102
申请日：1995-04-11
申请人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
发明人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
IPC分类号： H03M9/00 , H04L7/033 , H04L25/34
CPC分类号： H04L7/0338 , H03M9/00 , H04L7/005
摘要： A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.
摘要翻译：提供信号平滑和滤波功能以及滑动周期补偿的同步器和相位对准方法，并且允许多通道数字相位对准，总线偏移校正，在单个半导体芯片内集成多个收发器等。延迟线产生多个的输入信号的延迟输入副本。时钟相位调节器从参考时钟信号产生采样时钟信号。采样时钟信号可以被相位调整以偏离输入信号。经过一定的平滑和滤波功能后，选择逻辑检测采样时钟信号和输入副本之间的相位关系，并识别紧密同步的信号进行输出。使用该识别的复制信号，打滑周期补偿和重新定时逻辑输出与参考时钟信号同步的补偿数据输出信号。此外，提出了使用相位对准技术制造的集成多收发器。

4. 发明授权

US5533072A Digital phase alignment and integrated multichannel transceiver employing same 失效
公开(公告)号：US5533072A
公开(公告)日：1996-07-02
申请号：US152108
申请日：1993-11-12
申请人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
发明人： Christos J. Georgiou , Thor A. Larsen , Ki W. Lee
IPC分类号： H03M9/00 , H04L7/033 , H03D3/24
CPC分类号： H04L7/0338 , H03M9/00 , H04L7/005
摘要： A synchronizer and phase aligning method that provide signal smoothing and filtering functions as well as slip-cycle compensation, and allow for multichannel digital phase alignment, bus deskewing, integration of multiple transceivers within a single semiconductor chip, etc. A delay line produces a plurality of delayed input replicas of an input signal. A clock phase adjuster produces a sampling clock signal from a reference clock signal. The sampling clock signal may be phase adjusted to be offset from the input signal. After certain smoothing and filtering functions, selection logic detects a phase relationship between the sampling clock signal and the input replicas and identifies a closely synchronized signal for output. Using this identified replica signal, slip-cycle compensation and retiming logic outputs a compensated data output signal synchronized with the reference clock signal. Also, an integrated multiple transceiver produced using the phase alignment technique is presented.

5. 发明授权

US07574524B2 Method and system for on-demand allocation of a dynamic network of services 失效
标题翻译：动态服务网络按需分配的方法和系统
公开(公告)号：US07574524B2
公开(公告)日：2009-08-11
申请号：US10674962
申请日：2003-09-30
申请人： David F. Bantz , David M. Chess , Christos J. Georgiou , Jeffrey O. Kephart , Clifford A. Pickover
发明人： David F. Bantz , David M. Chess , Christos J. Georgiou , Jeffrey O. Kephart , Clifford A. Pickover
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L67/1008 , H04L67/1002 , H04L67/1029
摘要： A system and method for providing real-time, dynamic switching between first and second service providers each capable of providing a service for users over a communications network. The method includes steps of: establishing switching criterion for deciding when to switch service provision between the first service provider and second service provider; maintaining state information associated with a user's use of the service provided by a first service provider; switching between the first and second service provided over the communications network based on satisfaction of the switching criterion; and, migrating any state information maintained up to the time of switching to the second service. Preferably, the dynamic switching occurs in a manner substantially transparent to the user.
摘要翻译：一种用于在第一和第二服务提供商之间提供实时动态切换的系统和方法，每个服务提供商能够通过通信网络为用户提供服务。该方法包括以下步骤：建立用于决定何时切换第一服务提供商和第二服务提供商之间的服务提供的切换标准; 维护与用户对由第一服务提供商提供的服务的使用相关联的状态信息; 基于切换标准的满足，在通信网络上提供的第一和第二服务之间切换; 并且将维护的任何状态信息迁移到切换到第二服务的时间。优选地，动态切换以对用户基本透明的方式发生。

6. 发明授权

US5535213A Ring configurator for system interconnection using fully covered rings 失效
标题翻译：环形配置器，用于使用全覆盖环的系统互连
公开(公告)号：US5535213A
公开(公告)日：1996-07-09
申请号：US355862
申请日：1994-12-14
申请人： Shien-Tai Pan , Ting Cheng , Christos J. Georgiou , George W. Nation , Chung-Sheng Li
发明人： Shien-Tai Pan , Ting Cheng , Christos J. Georgiou , George W. Nation , Chung-Sheng Li
IPC分类号： H04L12/46 , H04L12/56 , H04J15/00
CPC分类号： H04L45/02 , H04L12/4637
摘要： A ring configurator for interconnection of data processing and communication systems uses fully covered rings. The ring configuration mechanism can be used to construct a set of covering rings preserving full connectivity for system interconnect. The mechanism can also be used for establishing the routing table for each interconnected system during the system initialization time. To generate a set of edge-disjoint rings, a rotational mechanism is used. The rings are considered stretching along a horizontal direction with nodes aligned in columns across all the rings. With a proper relabeling of the nodes, nodes appearing in the same column position of each ring can be obtained by a simple rotation of the nodes from the previous column of the rings. Once the rotational position is determined for each column, a set of N-1 edge-disjoint rings can be constructed. To find an extra ring so that when combined with the N-1 rings thus found the ring constraints are satisfied, a node reduction technique is invoked. The procedure can be repeated until a set of N edge-disjoint rings satisfying the constraints are found.
摘要翻译：用于数据处理和通信系统互连的环形配置器使用完全覆盖的环。环配置机制可用于构建一套保护系统互连的完整连接的覆盖环。该机制还可用于在系统初始化时间期间为每个互连系统建立路由表。为了产生一组边缘不相交的环，使用旋转机构。这些环被认为沿水平方向伸展，节点对齐在所有环上。通过对节点的适当重新标定，出现在每个环的相同列位置的节点可以通过从前一列的环的简单旋转获得。一旦为每列确定了旋转位置，就可以构造一组N-1个不相交的环。为了找到一个额外的环，使得当与N-1环组合时，因此发现环约束被满足，节点减少技术被调用。可以重复该过程，直到找到满足约束的一组N个边缘不相交的环。

7. 发明授权

US4845704A Switching system for integrated voice/data communications 失效
标题翻译：用于集成语音/数据通信的交换系统
公开(公告)号：US4845704A
公开(公告)日：1989-07-04
申请号：US33437
申请日：1987-04-01
申请人： Christos J. Georgiou , Gerald Lebizay
发明人： Christos J. Georgiou , Gerald Lebizay
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04Q11/04
摘要： A method of integrating the switching of voice and data between terminals connected to switch adapters. The switching of voice (or more generally synchronous signals) is accomplished by grouping voice samples in a first adapter and bound for the same destination or second adapter into a frame. Connections are then established between the two adapters and the frame is transmitted therethrough. A duplex method can also be set up by transmitting in both directions at the same time once a dual connection between the first and second adapter is established. Hence, a second group of voice samples bound for the first adapter is also formed ina frame. The two frames are then transmitted simultaneously in opposite directions through a dual connection in the switching matrix. Data is switched by storing data in respective memories of respective adapters, wherein each respective memory corresponds to a particular adapter to which the data stored therein is to be sent.

8. 发明授权

US08244880B2 Connection management method, system, and program product 失效
标题翻译：连接管理方法，系统和程序产品
公开(公告)号：US08244880B2
公开(公告)日：2012-08-14
申请号：US12191336
申请日：2008-08-14
申请人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
发明人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F12/0875 , G06F12/122 , H04L49/90 , H04L67/14 , H04L69/28
摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.
摘要翻译：本发明提供了一种用于管理连接的方法，系统和程序产品。特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

9. 发明授权

US08036243B2 Single chip protocol converter 失效
标题翻译：单芯片协议转换器
公开(公告)号：US08036243B2
公开(公告)日：2011-10-11
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

10. 发明授权

US5402416A Method and system for buffer occupancy reduction in packet switch network 失效
标题翻译：分组交换网络缓存占用率减少的方法和系统
公开(公告)号：US5402416A
公开(公告)日：1995-03-28
申请号：US177873
申请日：1994-01-05
申请人： Randall A. Cieslak , Christos J. Georgiou , Chung-Sheng Li
发明人： Randall A. Cieslak , Christos J. Georgiou , Chung-Sheng Li
IPC分类号： H04M7/00 , H04L12/56 , H04L12/64 , H04Q11/04
CPC分类号： H04L47/10 , H04L12/64
摘要： A packet switch system having a buffer occupancy reduction mechanism for controlling data flow through switched nodes of the system to avoid congestion and reduce required buffer storage at the nodes. For an isochronous connection, buffers are initially allocated at each switching node connection to ensure listless transmission of packets. A buffer occupancy trace for the connection is recorded and the delay time of an isochronous packet at a particular switch port is returned to a preceding switch port. The preceding switch port employs the feedback message to delay subsequent packets through the connection to reduce the queuing time at the particular switch port. Once the isochronous connection has stabilized, buffer reallocation is performed wherein a scheduler at each switch node along the connection attempts to combine buffer allocations for different isochronous connections. This occurs provided the corresponding buffer occupancy traces of the isochronous connections do not overlap. Buffer occupancy reduction is therefore accomplished through the delaying of isochronous packets propagated through the connections of the packet switch system and the reallocating of buffers initially assigned to two or more isochronous connections.
摘要翻译：一种分组交换系统，具有缓冲占用减少机制，用于控制通过系统的交换节点的数据流，以避免拥塞并减少节点处所需的缓冲存储。对于等时连接，最初在每个交换节点连接处分配缓冲区，以确保数据包的无干扰传输。记录连接的缓冲占用轨迹，并将特定交换机端口上的等时数据包的延迟时间返回到前一个交换机端口。上述交换机端口采用反馈消息来延迟通过连接的后续分组，以减少特定交换机端口的排队时间。一旦同步连接已经稳定，则执行缓冲器重新分配，其中沿着连接的每个交换节点处的调度器尝试组合用于不同等时连接的缓冲器分配。如果同步连接的相应缓冲区占用轨迹不重叠，则会发生这种情况。因此，通过延迟通过分组交换系统的连接传播的同步分组和最初分配给两个或多个同步连接的缓冲区的重新分配来实现缓冲器占用减少。

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