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1. 发明授权

US08217684B2 Fast and accurate current driver with zero standby current and features for boost and temperature compensation for MRAM write circuit 有权
标题翻译：具有零待机电流的快速准确的电流驱动器和用于MRAM写电路的升压和温度补偿功能
公开(公告)号：US08217684B2
公开(公告)日：2012-07-10
申请号：US12925004
申请日：2010-10-12
申请人： Perng-Fei Yuh , Pokang Wang , Lejan Pu , Minh Tran , Chao-Hung Chang
发明人： Perng-Fei Yuh , Pokang Wang , Lejan Pu , Minh Tran , Chao-Hung Chang
IPC分类号： H03B1/00
CPC分类号： G05F3/26 , G11C11/16 , G11C29/021 , G11C29/028
摘要： Systems and methods for realizing current drivers without current or voltage feedback for devices that require accurate current drive with zero standby current has been disclosed. In a preferred embodiment of the invention this current driver is applied for write circuits for MRAMs. A fast and accurate reference current is generated by diode voltage divided by resistor without any feedback. The diode current is not fed back from the reference current. The diode current is generated from a regulated voltage. Temperature compensation of the write current is inherently built in the diode current reference. Fine-tuning of the temperature coefficient is achieved by mixing poly and diffusion resistors. A switch inserted in the current driver can turn on the driver fast and without a need for standby current. Leading boost in the current driver can fast charge the large coupling capacitance of word and bit lines and speed up write timing.
摘要翻译：已经公开了用于实现没有电流或电压反馈的电流驱动器的系统和方法，用于需要具有零待机电流的精确电流驱动的装置。在本发明的优选实施例中，该电流驱动器被应用于MRAM的写入电路。通过二极管电压除以电阻而没有任何反馈产生快速准确的参考电流。二极管电流不从参考电流反馈。二极管电流由调节电压产生。写入电流的温度补偿固有地内置在二极管电流参考中。通过混合多聚电阻和扩散电阻来实现温度系数的微调。插入当前驱动程序的开关可快速打开驱动器，无需待机电流。当前驱动器的领先提升可以快速充电字和位线的大耦合电容，并加快写时序。

2. 发明申请

US20130176773A1 Reference Averaging for MRAM Sense Amplifiers 有权
标题翻译： MRAM检测放大器的参考平均
公开(公告)号：US20130176773A1
公开(公告)日：2013-07-11
申请号：US13345116
申请日：2012-01-06
申请人： Perng-Fei Yuh , Pokang Wang , Lejan Pu
发明人： Perng-Fei Yuh , Pokang Wang , Lejan Pu
IPC分类号： G11C11/02 , G11C7/06
CPC分类号： G11C7/06 , G11C11/1673 , G11C2207/063
摘要： A sense amplifier comprising a reference current developed from a programmed and a non-programmed reference cell is used to read a signal from a magnetic random access memory (MRAM) comprising magnetic tunnel junction (MTJ) cells. The average current is determined from reference cells in as few as one sense amplifier and as many as n sense amplifiers, and is an average current between the programmed reference cell and the non-programmed reference cell that approximates the mid point between the two states. The sense amplifier can be fully differential or a non differential sense amplifier.
摘要翻译：包括从编程和非编程参考单元产生的参考电流的读出放大器用于从包括磁性隧道结（MTJ）单元的磁性随机存取存储器（MRAM）读取信号。平均电流由少于1个读出放大器和多达n个读出放大器的参考单元确定，并且是编程参考单元和非编程参考单元之间的平均电流，其近似于两个状态之间的中点。读出放大器可以是全差分或非差分读出放大器。

3. 发明申请

US20120086476A1 Fast and accurate current driver with zero standby current and features for boost and temperature compensation for MRAM write circuit 有权
公开(公告)号：US20120086476A1
公开(公告)日：2012-04-12
申请号：US12925004
申请日：2010-10-12
申请人： Perng-Fei Yuh , Pokang Wang , Lejan Pu , Minh Tran , Chao-Hung Chang
发明人： Perng-Fei Yuh , Pokang Wang , Lejan Pu , Minh Tran , Chao-Hung Chang
IPC分类号： H03K3/00
CPC分类号： G05F3/26 , G11C11/16 , G11C29/021 , G11C29/028
摘要： Systems and methods for realizing current drivers without current or voltage feedback for devices that require accurate current drive with zero standby current has been disclosed. In a preferred embodiment of the invention this current driver is applied for write circuits for MRAMs. A fast and accurate reference current is generated by diode voltage divided by resistor without any feedback. The diode current is not fed back from the reference current. The diode current is generated from a regulated voltage. Temperature compensation of the write current is inherently built in the diode current reference. Fine-tuning of the temperature coefficient is achieved by mixing poly and diffusion resistors. A switch inserted in the current driver can turn on the driver fast and without a need for standby current. Leading boost in the current driver can fast charge the large coupling capacitance of word and bit lines and speed up write timing.

4. 发明授权

US07609543B2 Method and implementation of stress test for MRAM 有权
标题翻译： MRAM应力测试方法与实现
公开(公告)号：US07609543B2
公开(公告)日：2009-10-27
申请号：US11904434
申请日：2007-09-27
申请人： Hsu Kai Yang , Lejan Pu , Perng-Fei Yuh , Po-Kang Wang
发明人： Hsu Kai Yang , Lejan Pu , Perng-Fei Yuh , Po-Kang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C29/06 , G11C29/08 , G11C29/12005
摘要： Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.
摘要翻译：磁性随机存取存储器（MRAM）电池的电压和电流应力可以消除潜在的早期故障电池。用于MRAM的这种应力测试的方法和电路实现包括将应力测试电路耦合到MRAM的读总线，并通过激活与它们相关联的隔离晶体管将它们绑定到地来强调磁隧道接合点（MTJS）。读取字线控制哪些MTJ受到压力这两种方法和实现都可以用于基于电阻差异的任何存储单元，如相位RAM或自旋阀MRAM。

5. 发明申请

US20090086531A1 Method and implementation of stress test for MRAM 有权
公开(公告)号：US20090086531A1
公开(公告)日：2009-04-02
申请号：US11904434
申请日：2007-09-27
申请人： Hsu Kai Yang , Lejan Pu , Perng-Fei Yuh , Po-Kang Wang
发明人： Hsu Kai Yang , Lejan Pu , Perng-Fei Yuh , Po-Kang Wang
IPC分类号： G11C11/00 , G11C29/00
CPC分类号： G11C11/16 , G11C29/06 , G11C29/08 , G11C29/12005
摘要： Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

6. 发明授权

US08488357B2 Reference cell architectures for small memory array block activation 有权
标题翻译：小型存储器阵列块激活的参考单元结构
公开(公告)号：US08488357B2
公开(公告)日：2013-07-16
申请号：US12925492
申请日：2010-10-22
申请人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
发明人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
IPC分类号： G11C5/08
CPC分类号： G11C5/063 , G11C7/14 , G11C8/12 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675
摘要： Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
摘要翻译：已经实现了用于实现参考电流以提高分段半导体存储器阵列的感测操作的可靠性的系统和方法。本发明的优选实施例包括MRAM阵列，但是本发明可以应用于需要在小的分段阵列上访问的任何其他存储器。本发明的所有实施例包括在相邻位线中或在段到段折叠的位线中的折叠位线方案。在两个实施例中，通过读取字线和写入选择线的金属层实现了每个第二段中的多晶硅字线的交替捆扎。一个实施例在要读取的所选择的段的两侧上存储了1个和0个单元。

7. 发明申请

US20120099358A1 Reference cell architectures for small memory array block activation 有权
标题翻译：小型存储器阵列块激活的参考单元结构
公开(公告)号：US20120099358A1
公开(公告)日：2012-04-26
申请号：US12925492
申请日：2010-10-22
申请人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
发明人： Toshio Sunaga , Lejan Pu , Perng-Fei Yuh , Chao-Hung Chang
IPC分类号： G11C5/08 , G11C5/06
CPC分类号： G11C5/063 , G11C7/14 , G11C8/12 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C11/1675
摘要： Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
摘要翻译：已经实现了用于实现参考电流以提高分段半导体存储器阵列的感测操作的可靠性的系统和方法。本发明的优选实施例包括MRAM阵列，但是本发明可以应用于需要在小的分段阵列上访问的任何其他存储器。本发明的所有实施例包括在相邻位线中或在段到段折叠的位线中的折叠位线方案。在两个实施例中，通过读取字线和写入选择线的金属层实现了每个第二段中的多晶硅字线的交替捆扎。一个实施例在要读取的所选择的段的两侧上存储了1个和0个单元。

8. 发明授权

US08693273B2 Reference averaging for MRAM sense amplifiers 有权
标题翻译： MRAM读出放大器的参考平均
公开(公告)号：US08693273B2
公开(公告)日：2014-04-08
申请号：US13345116
申请日：2012-01-06
申请人： Perng-Fei Yuh , Po-Kang Wang , Lejan Pu
发明人： Perng-Fei Yuh , Po-Kang Wang , Lejan Pu
IPC分类号： G11C7/02
CPC分类号： G11C7/06 , G11C11/1673 , G11C2207/063
摘要： A sense amplifier comprising a reference current developed from a programmed and a non-programmed reference cell is used to read a signal from a magnetic random access memory (MRAM) comprising magnetic tunnel junction (MTJ) cells. The average current is determined from reference cells in as few as one sense amplifier and as many as n sense amplifiers, and is an average current between the programmed reference cell and the non-programmed reference cell that approximates the mid point between the two states. The sense amplifier can be fully differential or a non differential sense amplifier.
摘要翻译：包括从编程和非编程参考单元产生的参考电流的读出放大器用于从包括磁性隧道结（MTJ）单元的磁性随机存取存储器（MRAM）中读取信号。平均电流由少于1个读出放大器和多达n个读出放大器的参考单元确定，并且是编程参考单元和非编程参考单元之间的平均电流，其近似于两个状态之间的中点。读出放大器可以是全差分或非差分读出放大器。

9. 发明授权

US08605520B2 Replaceable, precise-tracking reference lines for memory products 有权
标题翻译：存储产品的可更换，精确跟踪参考线
公开(公告)号：US08605520B2
公开(公告)日：2013-12-10
申请号：US12924184
申请日：2010-09-22
申请人： Lejan Pu , Toshio Sunaga
发明人： Lejan Pu , Toshio Sunaga
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C8/14 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.
摘要翻译：已经实现了提高需要读取诸如MRAM或任何类型的相变存储器（PCM）的参考的半导体存储器阵列的感测操作的可靠性的系统和方法，并且提高了存储器阵列的产量。存储器阵列被分成多个部分，例如部分或部分。参考字线或参考位线或两者部署在多个部分的每一个中。因此，所访问的线路和通信参考线路之间的距离减小，因此寄生参数跟踪能力显着提高。另外备用参考字线或备用参考位线可以部署在多个部分的每一个中。

10. 发明申请

US20120069644A1 Replaceable, precise-tracking reference lines for memory products 有权
标题翻译：存储产品的可更换，精确跟踪参考线
公开(公告)号：US20120069644A1
公开(公告)日：2012-03-22
申请号：US12924184
申请日：2010-09-22
申请人： Lejan Pu , Toshio Sunaga
发明人： Lejan Pu , Toshio Sunaga
IPC分类号： G11C11/00 , G11C11/14 , G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C8/14 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2211/5634
摘要： Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.
摘要翻译：已经实现了提高需要读取诸如MRAM或任何类型的相变存储器（PCM）的参考的半导体存储器阵列的感测操作的可靠性的系统和方法，并且提高了存储器阵列的产量。存储器阵列被分成多个部分，例如部分或部分。参考字线或参考位线或两者部署在多个部分的每一个中。因此，所访问的线路和通信参考线路之间的距离减小，因此寄生参数跟踪能力显着提高。另外备用参考字线或备用参考位线可以部署在多个部分的每一个中。

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