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    • 3. 发明授权
    • Fast and accurate current driver with zero standby current and features for boost and temperature compensation for MRAM write circuit
    • 具有零待机电流的快速准确的电流驱动器和用于MRAM写电路的升压和温度补偿功能
    • US08217684B2
    • 2012-07-10
    • US12925004
    • 2010-10-12
    • Perng-Fei YuhPokang WangLejan PuMinh TranChao-Hung Chang
    • Perng-Fei YuhPokang WangLejan PuMinh TranChao-Hung Chang
    • H03B1/00
    • G05F3/26G11C11/16G11C29/021G11C29/028
    • Systems and methods for realizing current drivers without current or voltage feedback for devices that require accurate current drive with zero standby current has been disclosed. In a preferred embodiment of the invention this current driver is applied for write circuits for MRAMs. A fast and accurate reference current is generated by diode voltage divided by resistor without any feedback. The diode current is not fed back from the reference current. The diode current is generated from a regulated voltage. Temperature compensation of the write current is inherently built in the diode current reference. Fine-tuning of the temperature coefficient is achieved by mixing poly and diffusion resistors. A switch inserted in the current driver can turn on the driver fast and without a need for standby current. Leading boost in the current driver can fast charge the large coupling capacitance of word and bit lines and speed up write timing.
    • 已经公开了用于实现没有电流或电压反馈的电流驱动器的系统和方法,用于需要具有零待机电流的精确电流驱动的装置。 在本发明的优选实施例中,该电流驱动器被应用于MRAM的写入电路。 通过二极管电压除以电阻而没有任何反馈产生快速准确的参考电流。 二极管电流不从参考电流反馈。 二极管电流由调节电压产生。 写入电流的温度补偿固有地内置在二极管电流参考中。 通过混合多聚电阻和扩散电阻来实现温度系数的微调。 插入当前驱动程序的开关可快速打开驱动器,无需待机电流。 当前驱动器的领先提升可以快速充电字和位线的大耦合电容,并加快写时序。
    • 9. 发明授权
    • Buffered nondestructive-readout Josephson memory cell with three gates
    • 具有三个门的缓冲非破坏性读出约瑟夫逊记忆单元
    • US5229962A
    • 1993-07-20
    • US714447
    • 1991-06-13
    • Perng-Fei YuhEric Hanson
    • Perng-Fei YuhEric Hanson
    • G11C11/44H03K3/38
    • H03K3/38G11C11/44
    • A buffered nondestructive-readout Josephson memory cell comprises only three gates and is free of the half-select problem associated with Josephson memories, for both write and read operations. The basic memory cell unit comprises a first interferometer gate and an associated inductor defining a memory storage loop and a second interferometer gate that, together with a second inductor, defines a second loop in which a current pulse can be established only when a circulating current exists in the first loop. A third gate, responsive to a sense line and to the current pulse in the second loop, provides a voltage output which changes based upon whether a "1" or a "0" has been stored in the storage loop. For fabricating a bit-accessible memory, the third gate is further connected in closed circuit relationship with a third inductor which is magnetically coupled with the first gate.
    • 缓冲非破坏性读出约瑟夫逊存储器单元仅包含三个门,并且与写入和读取操作两者都不存在与约瑟夫逊存储器相关的半选择问题。 基本存储单元单元包括第一干涉仪栅极和限定存储器存储环路的相关电感器和第二干涉仪栅极,第二干涉仪栅极与第二电感器一起限定第二环路,其中仅当存在循环电流时才能建立电流脉冲 在第一个循环。 响应于感测线路和第二回路中的当前脉冲的第三门提供了基于存储回路中是否存储“1”或“0”而改变的电压输出。 为了制造可位置存储器,第三栅极进一步以与第一栅极磁耦合的第三电感器的闭路关系连接。