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    • 5. 发明申请
    • SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 自对准垂直非线性半导体存储器件
    • US20140167134A1
    • 2014-06-19
    • US13514032
    • 2012-02-02
    • Pengfei WangXi LinQingqing SunWei Zhang
    • Pengfei WangXi LinQingqing SunWei Zhang
    • H01L27/115
    • H01L27/11563G11C16/0475H01L21/84H01L27/1021H01L27/1026H01L27/1157H01L27/1203H01L29/7391H01L29/7923H01L29/8616
    • The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density.
    • 本发明属于半导体存储器件的技术领域,具体涉及一种自对准的垂直非易失性半导体存储器件,包括:半导体衬底,第一掺杂类型的漏极区域,第二掺杂型的两个源极区域, 用于捕获电子的堆叠栅; 其中漏极区域,两个源极区域和堆叠的栅极形成共享一个栅极和一个漏极的两个隧道场效应晶体管(TFET),每个TFET的漏极区域电流受到电荷的量和分布的影响 用于捕获电子的堆叠栅极,漏极埋在半导体衬底中,漏极区域上方的源极区域通过沟道与漏极分离,并通过第一掺杂类型的区域彼此分离。 本发明的半导体存储器件具有小的单位面积和简单的制造工艺。 使用本发明的存储芯片的制造成本低,存储密度高。
    • 6. 发明申请
    • SEMICONDUCTOR MEMORY STRUCTURE AND ITS MANUFACTURING METHOD THEREOF
    • 半导体存储器结构及其制造方法
    • US20140034891A1
    • 2014-02-06
    • US13376994
    • 2011-08-15
    • Pengfei WangXi LinQingqing SunWei Zhang
    • Pengfei WangXi LinQingqing SunWei Zhang
    • H01L27/24
    • H01L27/2463H01L27/2445H01L27/2472H01L29/7391H01L45/04H01L45/06H01L45/1233H01L45/144H01L45/146H01L45/1675
    • The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process.
    • 本发明属于微电子器件的技术领域,具体涉及一种半导体存储器结构及其制造方法。 形成通过隧道场效应晶体管对相变存储器或电阻变化存储器进行擦除,写入和读取操作的半导体存储器结构,一方面,当电流通过隧道场效应晶体管时, pn结积极偏置,满足擦除和写入相变存储器和电阻变化存储器的高电流要求,另一方面,场效应晶体管的垂直结构可以大大提高存储器件阵列的密度 。 本发明还公开了一种非常适用于存储芯片的方法,用于使用自对准工艺制造半导体存储器结构。
    • 7. 发明授权
    • Method for manufacturing semiconductor substrate of large-power device
    • 大功率器件半导体衬底的制造方法
    • US08557678B2
    • 2013-10-15
    • US13498144
    • 2011-11-18
    • Pengfei WangXi LinWei Zhang
    • Pengfei WangXi LinWei Zhang
    • H01L21/30H01L21/46
    • H01L29/66333H01L21/76275H01L29/41741
    • The invention belongs to the technical field of high-voltage, large-power devices and in particular relates to a method for manufacturing a semiconductor substrate of a large-power device. According to the method, the ion implantation is carried out on the front face of a floating zone silicon wafer first, then a high-temperature resistant metal is used as a medium to bond the back-off floating zone silicon wafer, and a heavily CZ-doped silicon wafer forms the semiconductor substrate. After bonding, the floating zone silicon wafer is used to prepare an insulated gate bipolar transistor (IGBT), and the heavily CZ-doped silicon wafer is used as the low-resistance back contact, so the required amount of the floating zone silicon wafers used is reduced, and production cost is lowered. Meanwhile, the back metallization process is not required after bonding, so the processing procedures are simplified, and the production yield is enhanced.
    • 本发明属于高压大功率器件的技术领域,特别涉及大功率器件的半导体衬底的制造方法。 根据该方法,首先在浮动区硅晶片的正面进行离子注入,然后使用耐高温金属作为介质来接合浮渣区硅晶片,并且重CZ 掺杂硅晶片形成半导体衬底。 在接合之后,使用浮动区硅晶片来制备绝缘栅双极晶体管(IGBT),并且将重CZ掺杂的硅晶片用作低电阻背接触,因此使用所需量的浮区硅晶片 降低了生产成本。 同时,接合后不需要背面金属化处理,因此简化了处理程序,并且提高了生产成品率。