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1. 发明申请

US20120261744A1 MICROELECTRONIC DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：微电子器件结构及其制造方法
公开(公告)号：US20120261744A1
公开(公告)日：2012-10-18
申请号：US13378114
申请日：2010-12-24
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/267 , H01L29/4236 , H01L29/513 , H01L29/66356 , H01L29/7391
摘要： The present invention refers to a semiconductor device especially a tunneling filed effect transistor (TFET) using narrow bandgap material as the source electrode material. A Semiconductor device which is a tunneling field effect transistor type semiconductor device, in which the source material is characterized as narrow band-gap material; meanwhile, there is a u-groove channel. The narrow band-gap material results in a raise of driving current and the u-groove channel reduced drain leakage current. The TFET disclosed in to present invention has the advantages of low leakage current, high drive current, and high integration density. The static power consumption is also reduced by using the present invention. The integration density is improved as well.
摘要翻译：本发明涉及使用窄带隙材料作为源电极材料的半导体器件，特别是隧道场效应晶体管（TFET）。作为隧道场效应晶体管型半导体器件的半导体器件，其中源材料被表征为窄带隙材料; 同时，还有一个U槽通道。窄带隙材料导致驱动电流的升高和U沟道沟道减少漏极漏电流。本发明公开的TFET具有漏电流低，驱动电流高，集成度高的优点。通过使用本发明，静电消耗也降低了。整合密度也提高了。

2. 发明申请

US20120309118A1 SILICON WAFER ALIGNMENT METHOD USED IN THROUGH-SILICON-VIA INTERCONNECTION 审中-公开
标题翻译：通过硅 - 互连方式使用的硅波对准方法
公开(公告)号：US20120309118A1
公开(公告)日：2012-12-06
申请号：US13304149
申请日：2011-11-23
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L21/66
CPC分类号： H01L25/0657 , H01L23/481 , H01L25/50 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06593
摘要： A method of silicon wafer alignment used in through-silicon-via interconnection for use in the field of high-integrity packaging technology is disclosed. In one aspect, the method includes aligning and calibrating the upper and lower silicon wafers, stacked and interconnected electrically, so as to improve alignment accuracy of silicon wafers and reduce interconnection resistances. In some embodiments, the integrated circuit chip made by the method improves speed and energy performance.
摘要翻译：公开了用于高完整性封装技术领域的硅通孔互连中使用的硅晶片对准方法。在一个方面，该方法包括对准和校准上下硅晶片，电子层叠和互连，以提高硅晶片的对准精度并降低互连电阻。在一些实施例中，通过该方法制造的集成电路芯片提高了速度和能量性能。

3. 发明授权

US08994095B2 Semiconductor memory device with a buried drain and its memory array 有权
标题翻译：具有埋地漏极及其存储器阵列的半导体存储器件
公开(公告)号：US08994095B2
公开(公告)日：2015-03-31
申请号：US13322640
申请日：2010-12-24
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L29/792 , H01L21/28 , H01L27/115
CPC分类号： H01L21/28273 , H01L27/11521
摘要： A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a, 101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.
摘要翻译：提供了一种具有埋地漏极的半导体存储器件。该器件包括半导体衬底（107）; 一个第一掺杂类型的漏极区域（108）; 具有第二掺杂类型的两个源极区域（101a，101b）以及设置在半导体基板上用于捕获电子的堆叠栅极。还提供了由多个半导体存储器件形成的存储器阵列及其制造方法。半导体存储器件具有电池面积小，制造工艺简单等优点。存储器件的制造成本降低，并且存储器件的存储密度增加。

4. 发明申请

US20120273866A1 Semiconductor Memory Device with a Buried Drain and Its Memory Array 有权
标题翻译：具有埋漏的半导体存储器件及其存储器阵列
公开(公告)号：US20120273866A1
公开(公告)日：2012-11-01
申请号：US13322640
申请日：2010-12-24
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , H01L27/11521
摘要： A semiconductor memory device with a buried drain is provided. The device comprises a semiconductor substrate (107); one drain region (108) of a first doping type; two source regions (101a,101b) of a second doping type; and a stacked gate provided on the semiconductor substrate for capturing electrons. A memory array formed by a plurality of semiconductor memory devices. and a manufacturing method thereof are also provided. The semiconductor memory device has the advantages of small cell area, simple manufacturing process and the like. The manufacturing cost of the memory device is reduced and the storing density of the memory device is increased.
摘要翻译：提供了一种具有埋地漏极的半导体存储器件。该器件包括半导体衬底（107）; 一个第一掺杂类型的漏极区域（108）; 具有第二掺杂类型的两个源极区域（101a，101b）以及设置在半导体基板上用于捕获电子的堆叠栅极。由多个半导体存储器件形成的存储器阵列。还提供了其制造方法。半导体存储器件具有电池面积小，制造工艺简单等优点。存储器件的制造成本降低，并且存储器件的存储密度增加。

5. 发明申请

US20120182063A1 Power Device Using Photoelectron Injection to Modulate Conductivity and the Method Thereof 审中-公开
标题翻译：使用光电子注入的功率器件调制电导率及其方法
公开(公告)号：US20120182063A1
公开(公告)日：2012-07-19
申请号：US13498778
申请日：2011-04-21
申请人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
发明人： Pengfei Wang , Qingqing Sun , Shijin Ding , Wei Zhang
IPC分类号： H01L31/167
CPC分类号： H01L31/1136 , H01L31/167
摘要： The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields.
摘要翻译：本发明属于半导体器件的技术领域，并且公开了使用光电子注入来调节电导率的功率器件及其方法。功率器件包括至少一个光电子注入光源和功率MOS晶体管。本发明使用光电子注入方法将载流子注入功率MOS晶体管的栅极下方的漂移区域，从而调制导电率并进一步降低功率MOS晶体管的比导通电阻。此外，随着漂移区域的掺杂浓度可以降低并且可以提高阻挡电压，可以大大提高功率MOS晶体管的性能，并且可以将功率MOS晶体管的应用扩展到高电压场。

6. 发明申请

US20140167134A1 SELF-ALIGNED VERTICAL NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：自对准垂直非线性半导体存储器件
公开(公告)号：US20140167134A1
公开(公告)日：2014-06-19
申请号：US13514032
申请日：2012-02-02
申请人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
IPC分类号： H01L27/115
CPC分类号： H01L27/11563 , G11C16/0475 , H01L21/84 , H01L27/1021 , H01L27/1026 , H01L27/1157 , H01L27/1203 , H01L29/7391 , H01L29/7923 , H01L29/8616
摘要： The present invention belongs to the technical field of semiconductor memory devices and specifically relates to a self-aligned vertical nonvolatile semiconductor memory device, Including: a semiconductor substrate, a drain region of a first doping type, two source regions of a second doping type, a stacked gate used to capture electrons; wherein the drain region, the two source regions and the stacked gate form two tunneling field effect transistors (TFETs) sharing one gate and one drain, the drain region current of each of the TFET is affected by the quantity and distribution of the charges in the stacked gate used to capture electrons, the drain is buried in the semiconductor substrate, the source regions above the drain region are separated from the drain through a channel and separated form each other through a region of the first doping type. The semiconductor memory device of the present invention features small unit area and simple manufacturing process. The memory chip using the present invention is of low manufacturing cost and high storage density.
摘要翻译：本发明属于半导体存储器件的技术领域，具体涉及一种自对准的垂直非易失性半导体存储器件，包括：半导体衬底，第一掺杂类型的漏极区域，第二掺杂型的两个源极区域，用于捕获电子的堆叠栅; 其中漏极区域，两个源极区域和堆叠的栅极形成共享一个栅极和一个漏极的两个隧道场效应晶体管（TFET），每个TFET的漏极区域电流受到电荷的量和分布的影响用于捕获电子的堆叠栅极，漏极埋在半导体衬底中，漏极区域上方的源极区域通过沟道与漏极分离，并通过第一掺杂类型的区域彼此分离。本发明的半导体存储器件具有小的单位面积和简单的制造工艺。使用本发明的存储芯片的制造成本低，存储密度高。

7. 发明申请

US20140034891A1 SEMICONDUCTOR MEMORY STRUCTURE AND ITS MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体存储器结构及其制造方法
公开(公告)号：US20140034891A1
公开(公告)日：2014-02-06
申请号：US13376994
申请日：2011-08-15
申请人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Qingqing Sun , Wei Zhang
IPC分类号： H01L27/24
CPC分类号： H01L27/2463 , H01L27/2445 , H01L27/2472 , H01L29/7391 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： The present invention belongs to the technical field of microelectronic devices, specifically relates to a semiconductor memory structure and its manufacturing method thereof. The semiconductor memory structure which carries out erasing, writing and reading operation on the phase change memory or the resistance change memory through a tunneling field-effect transistor is formed, for one hand, the high current passed through the tunneling field-effect transistor when the p-n junction the biased positively, meeting the high current requirements for erasing of and writing of the phase change memory and the resistance change memory, and on the other hand, Vertical structure of the field-effect transistor can greatly improve the density of memory devices arrays. The present invention also discloses a method, which is very suitable for the memory chips, for the manufacturing of the semiconductor memory structure using self-aligned process.
摘要翻译：本发明属于微电子器件的技术领域，具体涉及一种半导体存储器结构及其制造方法。形成通过隧道场效应晶体管对相变存储器或电阻变化存储器进行擦除，写入和读取操作的半导体存储器结构，一方面，当电流通过隧道场效应晶体管时， pn结积极偏置，满足擦除和写入相变存储器和电阻变化存储器的高电流要求，另一方面，场效应晶体管的垂直结构可以大大提高存储器件阵列的密度。本发明还公开了一种非常适用于存储芯片的方法，用于使用自对准工艺制造半导体存储器结构。

8. 发明授权

US08574958B2 Method for manufacturing a gate-control diode semiconductor memory device 有权
标题翻译：栅极控制二极管半导体存储器件的制造方法
公开(公告)号：US08574958B2
公开(公告)日：2013-11-05
申请号：US13535032
申请日：2012-06-27
申请人： Pengfei Wang , Xiaoyong Liu , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xiaoyong Liu , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/00
CPC分类号： H01L29/7391 , H01L29/8616
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor storage device. When the floating gate voltage is relatively high, the channel under the floating gate is of n type and a simple gate-control pn junction structure is configured; by controlling effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through a floating gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed while the quantity of charges in the floating gate determines the device threshold voltage, thus realizing memory functions. This invention features capacity of manufacturing gate-control diode memory devices able to reduce the chip power consumption through advantages of high driving current and small sub-threshold swing. This invention is applicable to semiconductor devices manufacturing based on flexible substrate and flat panel displays and floating gate memories, etc.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体存储器件的方法。当浮动栅极电压相对较高时，浮动栅极下的沟道为n型，并配置了简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过浮栅将n型ZnO反转为p型，并使用NiO作为p型半导体，形成npnp掺杂结构，浮动门中的电荷决定了器件的阈值电压，从而实现了存储器的功能。本发明具有制造栅极控制二极管存储器件的能力，其能够通过高驱动电流和小的次级阈值摆动的优点来降低芯片功耗。本发明适用于基于柔性基板和平板显示器和浮动栅极存储器等的半导体器件制造。

9. 发明申请

US20130178013A1 METHOD FOR MANUFACTURING A GATE-CONTROL DIODE SEMICONDUCTOR DEVICE 有权
标题翻译：制造门控二极管半导体器件的方法
公开(公告)号：US20130178013A1
公开(公告)日：2013-07-11
申请号：US13534983
申请日：2012-06-27
申请人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Chengwei Cao , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/34
CPC分类号： H01L29/22 , H01L29/66356 , H01L29/7391
摘要： This invention belongs to semiconductor device manufacturing field and discloses a method for manufacturing a gate-control diode semiconductor device. When the gate voltage is relatively high, the channel under the gate has an n type and the device has a simple gate-control pn junction structure; by way of controlling the effective n-type concentration of the ZnO film through back-gate control, inverting the n-type ZnO into p-type through the gate and using NiO as a p-type semiconductor, an n-p-n-p doping structure is formed. The present invention features capacity of manufacturing gate-control diode devices able to reduce the chip power consumption through the advantages of a high driving current and small sub-threshold swing, is especially applicable to the manufacturing of reading & writing devices having flat panel displays & phase change memory, and semiconductor devices based on flexible substrates.
摘要翻译：本发明属于半导体器件制造领域，并且公开了一种用于制造栅极控制二极管半导体器件的方法。当栅极电压相对较高时，栅极下方的沟道具有n型，器件具有简单的栅极控制pn结结构; 通过背栅控制来控制ZnO膜的有效n型浓度，通过栅极将n型ZnO转换成p型并使用NiO作为p型半导体，形成n-p-n-p掺杂结构。本发明特征在于能够通过高驱动电流和小的次阈值摆幅的优点来制造能够降低芯片功耗的栅极控制二极管器件的能力，特别适用于具有平板显示器的读写装置的制造，相变存储器以及基于柔性基板的半导体器件。

10. 发明申请

US20130149824A1 METHOD FOR MANUFACTURING A TUNNELING FIELD EFFECT TRANSISTOR WITH A U-SHAPED CHANNEL 有权
标题翻译：用U形通道制造隧道场效应晶体管的方法
公开(公告)号：US20130149824A1
公开(公告)日：2013-06-13
申请号：US13537956
申请日：2012-06-29
申请人： Pengfei Wang , Xi Lin , Wei Liu , Qingqing Sun , Wei Zhang
发明人： Pengfei Wang , Xi Lin , Wei Liu , Qingqing Sun , Wei Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/7391 , H01L29/0657 , H01L29/0895 , H01L29/517 , H01L29/66356
摘要： The present invention belongs to the technical field of semiconductor device manufacturing and specifically relates to a method for manufacturing a tunneling field effect transistor with a U-shaped channel. The U-shaped channel can effectively extend the transistor channel length, restrain the generation of leakage current in the transistor, and decrease the chip power consumption. The method for manufacturing a tunneling field effect transistor with a U-shaped channel put forward in the present invention is capable of realizing an extremely narrow U-shaped channel, overcoming the alignment deviation introduced by photoetching, and improving the chip integration degree.
摘要翻译：本发明属于半导体器件制造的技术领域，具体涉及一种具有U形沟道的隧道效应晶体管的制造方法。 U型通道可以有效地延长晶体管沟道长度，抑制晶体管中漏电流的产生，降低芯片功耗。本发明提出的具有U形通道的隧道场效应晶体管的制造方法能够实现非常窄的U形沟道，克服由光刻引入的取向偏差，提高芯片集成度。

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