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1. 发明授权

US4958312A Digital multiplier circuit and a digital multiplier-accumulator circuit which preloads and accumulates subresults 失效
标题翻译：数字乘法器电路和数字乘法器 - 累加器电路，其预加载和累加子结果
公开(公告)号：US4958312A
公开(公告)日：1990-09-18
申请号：US118496
申请日：1987-11-09
申请人： Peng-Huat Ang , Charles C. Stearns
发明人： Peng-Huat Ang , Charles C. Stearns
IPC分类号： G06F7/533 , G06F7/507 , G06F7/52 , G06F7/527 , G06F7/544
CPC分类号： G06F7/5318 , G06F7/5443 , G06F2207/3884 , G06F7/5338
摘要： Disclosed is a digital multiplier-accumulator circuit utilizing a carry save adder tree, pipeline register and carry select adder. Also disclosed is a digital multiplier circuit including a carry save adder tree and a pipeline register.

2. 发明授权

US4949295A Transformation of divisor and dividend in digital division 失效
标题翻译：数字师除数和股利变动
公开(公告)号：US4949295A
公开(公告)日：1990-08-14
申请号：US220768
申请日：1988-07-18
申请人： Charles C. Stearns
发明人： Charles C. Stearns
IPC分类号： G06F7/537 , G06F7/483 , G06F7/507 , G06F7/52 , G06F7/535
CPC分类号： G06F7/535 , G06F7/5375
摘要： A method to adjust the divisor and dividend, for application to a divider, so that the mantissa part of the divisor is transformed to be within a known limited range. The limiting of the transformed divisor range enables the complexity of the quotient select logic to be reduced accordingly. Once the divisor is restricted to the selected range, the dividend is adjusted proportionally so the quotient is unchanged.

3. 发明授权

US5774676A Method and apparatus for decompression of MPEG compressed data in a computer system 失效
标题翻译：用于在计算机系统中解压缩MPEG压缩数据的方法和装置
公开(公告)号：US5774676A
公开(公告)日：1998-06-30
申请号：US538887
申请日：1995-10-03
申请人： Charles C. Stearns , Stephanie W. Ti
发明人： Charles C. Stearns , Stephanie W. Ti
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50 , G06F17/00
CPC分类号： H04N21/4143 , H04N19/42 , H04N19/428 , H04N19/436 , H04N19/439 , H04N19/61 , H04N19/90
摘要： MPEG compressed data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator.
摘要翻译：在计算机系统中通过在计算机系统主机微处理器，图形加速器和专用MPEG处理器之间共享计算解压缩任务来解压缩MPEG压缩数据，以便最好地利用计算机系统中的资源。因此，专用MPEG处理器具有最小的能力，因此有利地是最小的成本。主机微处理器用于解压缩MPEG数据层。主机微处理器越强大，其解压缩的数据层越多。解压缩的其余部分（较低数据层）由MPEG专用处理器和/或图形加速器执行。

4. 发明授权

US5231601A Digital multiplier based upon a regularly structured sum of products adder array for partial product reduction 失效
标题翻译：数字乘法器基于定期结构化的乘积加法器阵列，用于部分乘积减少
公开(公告)号：US5231601A
公开(公告)日：1993-07-27
申请号：US827576
申请日：1992-01-28
申请人： Charles C. Stearns
发明人： Charles C. Stearns
IPC分类号： G06F7/52
CPC分类号： G06F7/5312 , G06F2207/3884 , G06F2207/3896
摘要： A digital multiplier is configured from a number of identical circuit "slices" with interconnecting signals arranged such that the need for large wiring channels is eliminated. The resulting multiplier, a hybrid of tree and array multipliers, has many of the space saving characteristics of array multipliers, with many of the speed advantages of tree multipliers. Various parameters of the design are flexible and may be changed by the designer to make speed versus size tradeoffs. The multiplier may be either pipelined or non-pipelined.
摘要翻译：数字乘法器由多个相同的电路“片”配置，互连信号布置成消除了对大布线通道的需要。结果乘法器是树和数组乘法器的混合，具有许多阵列乘法器的节省空间的特性，具有树乘法器的许多速度优势。设计的各种参数是灵活的，并且可以由设计者改变以使速度与尺寸的权衡。乘数可以是流水线或非流水线。

5. 发明授权

US5757670A Frame reconstruction for video data compression 失效
标题翻译：视频数据压缩的帧重构
公开(公告)号：US5757670A
公开(公告)日：1998-05-26
申请号：US508636
申请日：1995-07-28
申请人： Stephanie W. Ti , Charles C. Stearns
发明人： Stephanie W. Ti , Charles C. Stearns
IPC分类号： H04N19/89 , H04L9/34
CPC分类号： H04N19/577 , H04N19/59 , H04N19/61 , H04N19/85 , H04N19/89
摘要： The frame reconstruction (FR) portion of an MPEG decompression circuit includes a horizontal interpolation element, a vertical interpolation element, and a selector (post processing) element. The horizontal and vertical interpolation elements are each digital filters averaging respectively two horizontal and two vertical adjacent pixels in an MPEG pixel block. Logic is included for constructing B, I, and P-type MPEG pictures. Also included is an error/warning handling mechanism.
摘要翻译： MPEG解压缩电路的帧重建（FR）部分包括水平内插元素，垂直内插元素和选择器（后处理）元素。水平和垂直内插元素是在MPEG像素块中平均分别平均两个水平和两个垂直相邻像素的数字滤波器。包括用于构建B，I和P型MPEG图像的逻辑。还包括一个错误/警告处理机制。

6. 发明授权

US5719998A Partitioned decompression of audio data using audio decoder engine for computationally intensive processing 失效
标题翻译：使用音频解码器引擎对音频数据进行分区解压缩进行计算密集处理
公开(公告)号：US5719998A
公开(公告)日：1998-02-17
申请号：US489489
申请日：1995-06-12
申请人： Charlene S. Ku , Charles C. Stearns , Olive T. Tao
发明人： Charlene S. Ku , Charles C. Stearns , Olive T. Tao
IPC分类号： G10L19/02 , G06T9/00 , G10L19/00 , H03M7/30 , G10L7/04
CPC分类号： G06T9/007
摘要： Decompression of MPEG compressed audio data is performed in a computer system by the host processor in the computer system providing preprocessing data decompression and a dedicated audio decoder engine (which is a digital signal processor) performing the filtering and windowing of the host preprocessed data. The audio decoder engine includes a data path, instruction set, registers and internal program and data memory. The host performs a large portion of the audio decompression, leaving the windowing and filtering to the audio decoder engine. Thus the computationally intensive portions of the decompression are performed more efficiently. Coefficient storage in the audio decompression engine is optimized by taking advantage of the symmetries inherent in the coefficient data, both for the filter coefficients and the windowing coefficients. Double buffer input and output buffers speed the data flow between the host processor and the audio decoder engine. The double buffers allow a continuous flow of data from the host processor to the audio decoder engine.
摘要翻译：通过提供预处理数据解压缩的计算机系统中的主处理器和执行主机预处理数据的过滤和加窗的专用音频解码器引擎（其是数字信号处理器）在计算机系统中执行MPEG压缩音频数据的压缩。音频解码器引擎包括数据路径，指令集，寄存器以及内部程序和数据存储器。主机执行音频解压缩的大部分，将音频解码引擎的窗口化和过滤保留下来。因此，更有效地执行减压的计算密集部分。音频解压缩引擎中的系数存储器通过利用系数数据固有的对称性来优化滤波器系数和加窗系数。双缓冲器输入和输出缓冲器加速主处理器和音频解码器引擎之间的数据流。双缓冲器允许从主处理器到音频解码器引擎的数据的连续流动。

7. 发明授权

US5818967A Video decoder engine 失效
标题翻译：视频解码引擎
公开(公告)号：US5818967A
公开(公告)日：1998-10-06
申请号：US490322
申请日：1995-06-12
申请人： Soma Bhattacharjee , Charles C. Stearns
发明人： Soma Bhattacharjee , Charles C. Stearns
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50 , H04N21/2368 , H04N21/434 , H04N21/443 , G06K9/00 , G06K9/36 , G06K9/46 , G06K9/54
CPC分类号： H04N19/42 , H04N19/61 , H04N21/4143 , H04N21/426 , H04N21/42607
摘要： MPEG compressed video data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor (video decoder engine) in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator. The video decoder engine is a fast hardwired processor. It has a graceful degradation capability to allow dropping of occasional video frames without displaying any part of a dropped video frame. The video decoder engine has a three stage pipeline structure to minimize circuitry and speed up operation.
摘要翻译：在计算机系统中通过在计算机系统主机微处理器，图形加速器和专用MPEG处理器（视频解码器引擎）之间共享计算解压缩任务来解压缩MPEG压缩视频数据，以便最好地利用计算机系统中的资源。因此，专用MPEG处理器具有最小的能力，因此有利地是最小的成本。主机微处理器用于解压缩MPEG数据层。主机微处理器越强大，其解压缩的数据层越多。解压缩的其余部分（较低数据层）由MPEG专用处理器和/或图形加速器执行。视频解码器引擎是一种快速硬连线处理器。它具有优雅的降级能力，允许偶尔的视频帧丢弃，而不会显示丢弃的视频帧的任何部分。视频解码器引擎具有三级流水线结构，以最小化电路并加速操作。

8. 发明授权

US5778096A Decompression of MPEG compressed data in a computer system 失效
标题翻译：在计算机系统中压缩MPEG压缩数据
公开(公告)号：US5778096A
公开(公告)日：1998-07-07
申请号：US489488
申请日：1995-06-12
申请人： Charles C. Stearns
发明人： Charles C. Stearns
IPC分类号： G06T9/00 , H04N7/26 , H04N7/50 , G06K9/36 , G06K9/46
CPC分类号： H04N21/4143 , H04N19/42 , H04N19/428 , H04N19/436 , H04N19/439 , H04N19/61 , H04N19/90
摘要： MPEG compressed data is decompressed in a computer system by sharing computational decompression tasks between the computer system host microprocessor, the graphics accelerator, and a dedicated MPEG processor in order to make best use of resources in the computer system. Thus the dedicated MPEG processor is of minimum capability and hence advantageously minimum cost. The host microprocessor is used to decompress the MPEG upper data layers. The more powerful the host microprocessor, the more upper data layers it decompresses. The remainder of the decompression (lower data layers) is performed by the MPEG dedicated processor and/or the graphics accelerator.
摘要翻译：在计算机系统中通过在计算机系统主机微处理器，图形加速器和专用MPEG处理器之间共享计算解压缩任务来解压缩MPEG压缩数据，以便最好地利用计算机系统中的资源。因此，专用MPEG处理器具有最小的能力，因此有利地是最小的成本。主机微处理器用于解压缩MPEG数据层。主机微处理器越强大，其解压缩的数据层越多。解压缩的其余部分（较低数据层）由MPEG专用处理器和/或图形加速器执行。

9. 发明授权

US5715385A Apparatus for 2-D affine transformation of images 失效
标题翻译： 2-D仿射变换图像的装置
公开(公告)号：US5715385A
公开(公告)日：1998-02-03
申请号：US254150
申请日：1994-06-06
申请人： Charles C. Stearns , Karthikeyan Kannappan
发明人： Charles C. Stearns , Karthikeyan Kannappan
IPC分类号： G06T3/00
CPC分类号： G06T3/00
摘要： Affine image transformations are performed in an interleaved manner, whereby coordinate transformations and intensity calculations are alternately performed incrementally on small portions of an image. The pixels are processed in rows such that after coordinates of a first pixel are determined for reference, each pixel in a row, and then pixels in vertically adjacent rows, are processed relative to the coordinates of the previously processed adjacent pixels. After coordinate transformation to produce affine translation, rotation, skew and/or scaling, intermediate metapixels are vertically split and shifted to eliminate holes and overlaps. Intensity values of output metapixels are calculated as being proportional to the sum of scaled portions of the intermediate metapixels which cover the output pixels respectively.
摘要翻译：以交错方式执行仿射图像变换，由此在图像的小部分上交替执行坐标变换和强度计算。以行为处理像素，使得在确定第一像素的坐标以供参考之后，相对于先前处理的相邻像素的坐标来处理一行中的每个像素以及随后的垂直相邻行中的像素。在进行坐标变换以产生仿射平移，旋转，偏斜和/或缩放之后，中间像素垂直分割并移位以消除孔和重叠。输出像素的强度值被计算为与分别覆盖输出像素的中间像素的缩放部分的总和成比例。

10. 发明授权

US5539682A Seed generation technique for iterative, convergent digital computations 失效
标题翻译：用于迭代，收敛数字计算的种子生成技术
公开(公告)号：US5539682A
公开(公告)日：1996-07-23
申请号：US175497
申请日：1993-12-30
申请人： Himanshu Jain , Charles C. Stearns
发明人： Himanshu Jain , Charles C. Stearns
IPC分类号： G06F1/035 , G06F7/52 , G06F7/535 , G06F7/552 , G06F7/00 , G06F7/38
CPC分类号： G06F7/535 , G06F1/035 , G06F7/5525 , G06F2101/08 , G06F2101/12 , G06F2207/5355 , G06F7/4873
摘要： A novel technique for improving the accuracy of seed values for iterative convergent computations such as square-root taking and division by providing optional dynamic range expansion as a part of the seed selection process is described. The technique, by improving seed accuracy, reduces the number of iterations required for convergence. This is accomplished with less hardware than would be required to accomplish the same result with a large ROM.
摘要翻译：描述了通过提供可选的动态范围扩展作为种子选择过程的一部分来提高用于迭代收敛计算的种子值的准确性的新技术，例如平方根获取和除法。该技术通过提高种子准确度，减少了收敛所需的迭代次数。这是通过使用较少的硬件来实现的，而不是用大的ROM来完成相同的结果所需要的硬件。

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