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1. 发明申请

US20060035474A1 Increasing retention time for memory devices 审中-公开
标题翻译：增加存储设备的保留时间
公开(公告)号：US20060035474A1
公开(公告)日：2006-02-16
申请号：US10914827
申请日：2004-08-10
申请人： Pavel Komilovich , James Stasiak
发明人： Pavel Komilovich , James Stasiak
IPC分类号： H01L21/31 , H01L51/40 , H01L21/82 , H01L21/00
CPC分类号： G11C13/00 , G11C13/0014 , G11C13/0016 , H01L27/285
摘要： This disclosure relates to a doped polymer memory device. In one aspect the doped polymer memory device includes a molecularly doped polymer layer that includes a binder and a dopant. The combination of the binder and the dopant modifies polarizability of the molecularly doped polymer layer in a manner that enhances the retention time of the doped polymer memory device. In another aspect, the doped polymer memory device includes a molecularly doped polymer layer that includes a binder and a dopant. An additional dopant is added to the molecularly doped polymer layer. The additional dopant is selected to modify polarizability of the molecularly doped polymer layer in a manner that enhances the retention time of the doped polymer memory device.
摘要翻译：本公开涉及掺杂聚合物存储器件。在一个方面，掺杂聚合物存储器件包括分子掺杂的聚合物层，其包括粘合剂和掺杂剂。粘合剂和掺杂剂的组合以增加掺杂聚合物存储器件的保留时间的方式改变分子掺杂聚合物层的极化率。在另一方面，掺杂聚合物记忆装置包括分子掺杂的聚合物层，其包括粘合剂和掺杂剂。向分子掺杂的聚合物层中加入另外的掺杂剂。选择附加的掺杂剂以改善掺杂聚合物存储器件的保留时间的方式来改变分子掺杂聚合物层的极化率。

2. 发明申请

US20070007518A1 Encapsulation of nano-dimensional structures by oxidation 有权
标题翻译：通过氧化封装纳米尺寸结构
公开(公告)号：US20070007518A1
公开(公告)日：2007-01-11
申请号：US11174896
申请日：2005-07-05
申请人： Peter Mardilovich , Pavel Komilovich , Randy Hoffman
发明人： Peter Mardilovich , Pavel Komilovich , Randy Hoffman
IPC分类号： H01L29/10
CPC分类号： B81B1/00
摘要： This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited material becomes substantially encapsulated by a portion of the oxidized layer.
摘要翻译：本发明涉及一种封装纳米尺寸结构的方法，包括：在衬底上沉积至少一种材料，使得该材料包括至少一部分; 以及产生基本上邻近沉积材料定位的氧化层，使得沉积材料的至少一部分基本上被氧化层的一部分包封。

3. 发明申请

US20070241413A1 Field-Effect-Transistor Multiplexing/Demultiplexing Architectures and Methods of Forming The Same 有权
标题翻译：场效应晶体管复用/解复用架构及其形成方法
公开(公告)号：US20070241413A1
公开(公告)日：2007-10-18
申请号：US11765374
申请日：2007-06-19
申请人： Xiaofeng Yang , Pavel Komilovich
发明人： Xiaofeng Yang , Pavel Komilovich
IPC分类号： H01L27/105 , H01L21/336
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1203
摘要： This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.
摘要翻译：本公开涉及场效应晶体管（FET）复用/解复用架构及其制造方法。这些FET多路复用/多路分解结构之一使得能够对紧密调节的导电结构阵列进行解码。另一种能够有效地解码各种类型的导电结构阵列，紧密地倾斜或以其它方式。此外，公开了用于形成FET多路复用/多路分解结构的处理，其使用与取向无关的处理步骤。这些过程之一使用一个低精度压印步骤和进一步的取向非依赖性处理步骤。

4. 发明申请

US20050245014A1 Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same 有权
标题翻译：场效应晶体管复用/解复用架构及其形成方法
公开(公告)号：US20050245014A1
公开(公告)日：2005-11-03
申请号：US10835659
申请日：2004-04-30
申请人： Xiaofeng Yang , Pavel Komilovich
发明人： Xiaofeng Yang , Pavel Komilovich
IPC分类号： H01L21/8234 , H01L21/84 , H01L27/02 , H01L27/088 , H01L27/108 , H01L27/12 , H04L12/56
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1203
摘要： This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.
摘要翻译：本公开涉及场效应晶体管（FET）复用/解复用架构及其制造方法。这些FET多路复用/多路分解结构之一使得能够对紧密调节的导电结构阵列进行解码。另一种能够有效地解码各种类型的导电结构阵列，紧密地倾斜或以其它方式。此外，公开了用于形成FET多路复用/多路分解结构的处理，其使用与取向无关的处理步骤。这些过程中的一个使用一个低精度压印步骤和进一步的对准非依赖性处理步骤。

5. 发明授权

US07633098B2 Field-effect-transistor multiplexing/demultiplexing architectures 有权
标题翻译：场效应晶体管复用/解复用架构
公开(公告)号：US07633098B2
公开(公告)日：2009-12-15
申请号：US11765374
申请日：2007-06-19
申请人： Xiaofeng Yang , Pavel Komilovich
发明人： Xiaofeng Yang , Pavel Komilovich
IPC分类号： H01L27/10
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1203
摘要： This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.
摘要翻译：本公开涉及场效应晶体管（FET）复用/解复用架构及其制造方法。这些FET多路复用/多路分解结构之一使得能够对紧密调节的导电结构阵列进行解码。另一种能够有效地解码各种类型的导电结构阵列，紧密地倾斜或以其它方式。此外，公开了用于形成FET多路复用/多路分解结构的处理，其使用与取向无关的处理步骤。这些过程之一使用一个低精度压印步骤和进一步的取向非依赖性处理步骤。

6. 发明授权

US07381658B2 Encapsulation of nano-dimensional structures by oxidation 有权
标题翻译：通过氧化封装纳米尺寸结构
公开(公告)号：US07381658B2
公开(公告)日：2008-06-03
申请号：US11174896
申请日：2005-07-05
申请人： Peter Mardilovich , Pavel Komilovich , Randy Hoffman
发明人： Peter Mardilovich , Pavel Komilovich , Randy Hoffman
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： B81B1/00
摘要： This invention relates to a method of encapsulating nano-dimensional structures, comprising: depositing at least one material upon a substrate such that the material includes at least one portion; and creating an oxidized layer located substantially adjacent to the deposited material such that the at least one portion of the deposited material becomes substantially encapsulated by a portion of the oxidized layer.
摘要翻译：本发明涉及一种封装纳米尺寸结构的方法，包括：在衬底上沉积至少一种材料，使得该材料包括至少一部分; 以及产生基本上邻近沉积材料定位的氧化层，使得沉积材料的至少一部分基本上被氧化层的一部分包封。

7. 发明授权

US07247531B2 Field-effect-transistor multiplexing/demultiplexing architectures and methods of forming the same 有权
标题翻译：场效应晶体管复用/解复用架构及其形成方法
公开(公告)号：US07247531B2
公开(公告)日：2007-07-24
申请号：US10835659
申请日：2004-04-30
申请人： Xiaofeng Yang , Pavel Komilovich
发明人： Xiaofeng Yang , Pavel Komilovich
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/84 , H01L27/0207 , H01L27/1203
摘要： This disclosure relates to field-effect-transistor (FET) multiplexing/demultiplexing architectures and methods for fabricating them. One of these FET multiplexing/demultiplexing architectures enables decoding of an array of tightly pitched conductive structures. Another enables efficient decoding of various types of conductive-structure arrays, tightly pitched or otherwise. Also, processes for forming FET multiplexing/demultiplexing architectures are disclosed that use alignment-independent processing steps. One of these processes uses one, low-accuracy imprinting step and further alignment-independent processing steps.
摘要翻译：本公开涉及场效应晶体管（FET）复用/解复用架构及其制造方法。这些FET多路复用/多路分解结构之一使得能够对紧密调节的导电结构阵列进行解码。另一种能够有效地解码各种类型的导电结构阵列，紧密地倾斜或以其它方式。此外，公开了用于形成FET多路复用/多路分解结构的处理，其使用与取向无关的处理步骤。这些过程之一使用一个低精度压印步骤和进一步的取向非依赖性处理步骤。

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