专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090293023A1 Generation of standard cell library components with increased signal routing resources 有权
标题翻译：生成具有增加的信号路由资源的标准单元库组件
公开(公告)号：US20090293023A1
公开(公告)日：2009-11-26
申请号：US12124162
申请日：2008-05-21
申请人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
发明人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
摘要翻译：生成具有增加信号路由资源的单元。在一个实施例中，识别和去除源电池的金属层中的电源和接地总线。终止于已拆卸总线上的任何通孔也可以被去除。额外的通道和连接被添加到其他所需的层，以提供与由于较早的移除而断开的节点的连接。根据本发明的一个方面，在芯片设计阶段（即，当将单元实例结合到集成电路中时，这些连接被设计成）被添加。

2. 发明授权

US07895551B2 Generation of standard cell library components with increased signal routing resources 有权
标题翻译：生成具有增加的信号路由资源的标准单元库组件
公开(公告)号：US07895551B2
公开(公告)日：2011-02-22
申请号：US12124162
申请日：2008-05-21
申请人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
发明人： Dharin Shah , Clive David Bittlestone , Graham McLeod Barr , Girishankar Gurumurthy , Pavan Vithal Torvi
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Generating cells with increased signal routing resources. In an embodiment, power and ground buses in a metal layer of a source cell are identified and removed. Any vias terminating on the removed buses may also be removed. Additional via and connections are added to other desired layers to provide connectivity to the nodes disconnected due to the earlier removal. According to an aspect of the present invention, such connections are added during a chip design phase (i.e., when the cell instances are incorporated into an integrated circuit, sought to be designed).
摘要翻译：生成具有增加信号路由资源的单元。在一个实施例中，识别和去除源电池的金属层中的电源和接地总线。终止于已拆卸总线上的任何通孔也可以被去除。额外的通道和连接被添加到其他所需的层，以提供与由于较早的移除而断开的节点的连接。根据本发明的一个方面，在芯片设计阶段（即，当将单元实例结合到集成电路中时，这些连接被设计成）被添加。

3. 发明授权

US06374325B1 Content addressable memory (CAM) 有权
标题翻译：内容可寻址存储器（CAM）
公开(公告)号：US06374325B1
公开(公告)日：2002-04-16
申请号：US09251517
申请日：1999-02-17
申请人： Richard David Simpson , Laura Simmonite , Graham McLeod Barr
发明人： Richard David Simpson , Laura Simmonite , Graham McLeod Barr
IPC分类号： G06F1200
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) system (50) is disclosed which includes a CAM array (52) for storing an array of data words. More than one data word is stored on each row with the bits of the data word columns interleaved with each other. The CAM array (52) is accessed during one of several modes of operation in accordance with signals from a bit line controller (54) which activate certain ones of a plurality of bit lines coupling the bit line controller (54) to the CAM array (52). The modes of operation, as indicated by a mode control signal, include a write mode, a read mode and a match mode. In first embodiment of the present invention, the bit line controller (54) sequentially accesses each of the columns of data words by selectively activating certain of the bit lines in accordance with a column address signal and the mode control signal.
摘要翻译：公开了一种内容可寻址存储器（CAM）系统（50），其包括用于存储数据字阵列的CAM阵列（52）。每行上存储有多个数据字，数据字列的位彼此交错。根据来自位线控制器（54）的信号，几个操作模式之一访问CAM阵列（52），该位线控制器激活将位线控制器（54）耦合到CAM阵列的多个位线中的某些位线 52）。如模式控制信号所示的操作模式包括写入模式，读取模式和匹配模式。在本发明的第一实施例中，位线控制器（54）通过根据列地址信号和模式控制信号选择性地激活某些位线来顺序访问数据字中的每一列。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式