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    • 1. 发明授权
    • Method and apparatus for compensating DC level in an adaptive radio receiver
    • 用于在自适应无线电接收机中补偿直流电平的方法和装置
    • US07684775B2
    • 2010-03-23
    • US11601897
    • 2006-11-20
    • Jussi VepsäläinenAarno PärssinenPauli SeppinenMikael Gustafsson
    • Jussi VepsäläinenAarno PärssinenPauli SeppinenMikael Gustafsson
    • H04B1/10
    • H04B1/30
    • A radio frequency receiver 30, 32, includes a first component block 12, 16, 18, 20; a second compensating component block 22, 22a-22b, 34; and control circuitry 26 operable for controlling the state (e.g., load, bias, gain) of the first component block. When the control circuitry 26 causes a change in the state of the first component block that is expected to induce a DC offset in a signal, the control circuitry 26 changes the state of the second component block to compensate for an estimate of the DC offset. Preferably, the second component block is a filter 22, 22a-22b, 34, that temporarily changes from a nominal cutoff frequency to an elevated cutoff frequency so that voltage will settle quickly and accurately at an estimated voltage, the estimated voltage being predetermined and based on the state change to the first component block. A method is also described for practicing the invention.
    • 射频接收器30,32包括第一组件块12,16,18,20; 第二补偿部件块22,22a-22b,34; 以及可操作用于控制第一组件块的状态(例如,负载,偏置,增益)的控制电路26。 当控制电路26导致预期在信号中引起DC偏移的第一分量块的状态改变时,控制电路26改变第二分量块的状态以补偿DC偏移的估计。 优选地,第二组件块是过滤器22,22a-22b,34,暂时从标称截止频率改变到提升的截止频率,使得电压将在估计的电压下快速且准确地稳定,估计的电压是预定的并且基于 将状态更改为第一个组件块。 还描述了一种用于实施本发明的方法。
    • 2. 发明授权
    • Method and apparatus for compensating DC level in an adaptive radio receiver
    • 用于在自适应无线电接收机中补偿直流电平的方法和装置
    • US07139542B2
    • 2006-11-21
    • US10378172
    • 2003-03-03
    • Jussi VepsäläinenAarno PärssinenPauli SeppinenMikael Gustafsson
    • Jussi VepsäläinenAarno PärssinenPauli SeppinenMikael Gustafsson
    • H04B1/10
    • H04B1/30
    • A radio frequency receiver 30, 32, includes a first component block 12, 16, 18, 20; a second compensating component block 22, 22a–22b, 34; and control circuitry 26 operable for controlling the state (e.g., load, bias, gain) of the first component block. When the control circuitry 26 causes a change in the state of the first component block that is expected to induce a DC offset in a signal, the control circuitry 26 changes the state of the second component block to compensate for an estimate of the DC offset. Preferably, the second component block is a filter 22, 22a–22b, 34, that temporarily changes from a nominal cutoff frequency to an elevated cutoff frequency so that voltage will settle quickly and accurately at an estimated voltage, the estimated voltage being predetermined and based on the state change to the first component block. A method is also described for practicing the invention.
    • 射频接收器30,32包括第一组件块12,16,18,20; 第二补偿部件块22,22a-22b,34; 以及可操作用于控制第一组件块的状态(例如,负载,偏置,增益)的控制电路26。 当控制电路26导致预期在信号中引起DC偏移的第一分量块的状态改变时,控制电路26改变第二分量块的状态以补偿DC偏移的估计。 优选地,第二组件块是过滤器22,22a-22b,34,其临时从标称截止频率改变到提升的截止频率,使得电压将在估计的电压下快速且准确地稳定,所估计的电压是预定的 并且基于对第一组件块的状态改变。 还描述了一种用于实施本发明的方法。
    • 4. 发明授权
    • Method and device for digital-to-analog conversion with filtering
    • 用于通过滤波进行数模转换的方法和装置
    • US07812751B2
    • 2010-10-12
    • US11904510
    • 2007-09-26
    • Petri T. ElorantaPauli SeppinenAarno Pärssinen
    • Petri T. ElorantaPauli SeppinenAarno Pärssinen
    • H03M1/66
    • H03M1/745H03H15/00
    • The invention relates to a device and a method for converting a digital signal having a plurality of data-bits into a filtered analog signal. A device according to the invention includes a delay element arranged to produce one or more differently delayed version of the digital signal and a digital-to-analog conversion circuitry arranged to convert the digital signal and the one or more differently delayed, and possibly differently scaled, versions of the digital signal into analog signals and to produce the filtered analog signal as a combination of the analog signals. Therefore, the device constitutes not only a digital-to-analog-converter but also a finite impulse response filter.
    • 本发明涉及一种用于将具有多个数据位的数字信号转换为经滤波的模拟信号的装置和方法。 根据本发明的装置包括布置成产生数字信号的一个或多个不同延迟版本的延迟元件和被配置为转换数字信号和一个或多个不同延迟且可能不同的缩放的数模转换电路 ,将数字信号的版本转换成模拟信号,并产生滤波后的模拟信号作为模拟信号的组合。 因此,器件不仅构成了数模转换器,而且构成了有限的脉冲响应滤波器。
    • 10. 发明授权
    • Method and circuit for sampling a signal at high sampling frequency
    • 采样频率高的信号采样方法和电路
    • US06438366B1
    • 2002-08-20
    • US09316357
    • 1999-05-21
    • Saska LindforsAarno PärssinenKari Halonen
    • Saska LindforsAarno PärssinenKari Halonen
    • H03H1702
    • H03H19/004H03H17/0291
    • Electrical circuit (300, 500, 800, 900) has an input (301, 501, 801, 802, 901, 902) and an output (311, 502, OUT, I-OUT, Q-OUT). The circuit samples an input signal coupled to the input having a certain input frequency and converts the input signal into a certain output frequency at the output, the output frequency being lower than the input frequency. It comprises a first sampler circuit (302, 510, 803, 910) coupled to the input, a second sampler circuit (303, 520, 804, 920) coupled to the input, a buffering component (309, 509, 809, 903, 904) coupled to the output and buffer switching means (305-307, 514, 515, 811-818, 914, 915, 924, 925, 934, 935, 944, 945, 954, 955, 964, 965, 974, 975, 984, 985). The buffer switching means are arranged to respond to a buffering command (fs/N, A, B) by coupling said first sampler circuit and said second sampler circuit to said buffering component.
    • 电路(300,500,800,900)具有输入(301,501,801,802,901,902)和输出(311,502,OUT,I-OUT,Q-OUT)。 电路对耦合到具有一定输入频率的输入的输入信号进行采样,并将输入信号转换成输出端的某一输出频率,输出频率低于输入频率。 它包括耦合到输入的第一采样器电路(302,510,803,910),耦合到输入的第二采样器电路(303,520,804,920),缓冲部件(309,509,809,903,904) )耦合到输出和缓冲器切换装置(305-307,514,515,811-818,914,915,924,925,934,935,944,945,954,955,964,965,974,975,984,984 缓冲器切换装置被布置成通过将所述第一采样器电路和所述第二采样器电路耦合到所述缓冲部件来响应缓冲命令(fs / N,A,B)。