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1. 发明授权

US06600959B1 Method and apparatus for implementing microprocessor control logic using dynamic programmable logic arrays 失效
标题翻译：使用动态可编程逻辑阵列实现微处理器控制逻辑的方法和装置
公开(公告)号：US06600959B1
公开(公告)日：2003-07-29
申请号：US09498934
申请日：2000-02-04
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Brian King Flachs , Harm Peter Hofstee , Jaehong Park , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G05B1918
CPC分类号： H03K17/693 , H03K5/06
摘要： A method and apparatus for using dynamic programmable logic arrays in microprocessor control logic provide decreased power and increased clock frequencies for data processing systems, by using programmable logic arrays exclusively for the control logic. The method and apparatus further simplify the design of the control logic and closure of timing within the microprocessor, by providing overlap of control logic evaluations and data transfers within the microprocessor.
摘要翻译：在微处理器控制逻辑中使用动态可编程逻辑阵列的方法和装置通过专门用于控制逻辑的可编程逻辑阵列来为数据处理系统提供降低的功率和增加的时钟频率。该方法和装置通过在微处理器内提供控制逻辑评估和数据传输的重叠来进一步简化控制逻辑的设计和微处理器内的定时闭合。

2. 发明授权

US06294929B1 Balanced-delay programmable logic array and method for balancing programmable logic array delays 有权
标题翻译：平衡延迟可编程逻辑阵列和平衡可编程逻辑阵列延迟的方法
公开(公告)号：US06294929B1
公开(公告)日：2001-09-25
申请号：US09443205
申请日：1999-11-18
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Jaehong Park , Stephen Douglas Posluszny , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Jaehong Park , Stephen Douglas Posluszny , Osamu Takahashi
IPC分类号： H03K19177
CPC分类号： H03K19/17712
摘要： Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.
摘要翻译：平衡延迟可编程逻辑阵列和用于平衡可编程逻辑阵列延迟的方法在采用可编程逻辑的电路中提供改进的性能。通过将晶体管添加到不构成逻辑实现的一部分的编程平面，可以平衡每个输入逻辑线上的电容，从而大大减少进入最终逻辑门的信号之间的偏移。这提供了可编程逻辑阵列，可以在以前禁止偏移的应用中实现异步逻辑，并进一步提高了同步逻辑中的状态评估的可靠性。

3. 发明授权

US06232798B1 Self-resetting circuit timing correction 失效
标题翻译：自复位电路定时校正
公开(公告)号：US06232798B1
公开(公告)日：2001-05-15
申请号：US09457938
申请日：1999-12-09
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K1900
CPC分类号： H03K19/0966
摘要： A system and method with a self-reset circuit for synchronizing an input data path with a timing control path. The self-resetting circuit includes a normal-mode input detect circuit which detects an arrival of data from the input data path into the self-reset circuit and generates a normal-mode control signal in response thereto. The self-resetting circuit also includes a delay-mode input detect circuit for detecting the arrival of the data from the input data path and which generates a delay-mode control signal in response thereto. A toggle circuit is provided for disabling the normal-mode input detect circuit while simultaneously enabling the delay-mode input detect circuit. In response to the toggle circuit disabling the normal-mode input detect circuit, the delay-mode control signal propagates through a delay gate, such that said delay-mode control signal synchronizes said timing control path with respect to said data input path.
摘要翻译：一种具有用于使输入数据路径与定时控制路径同步的自复位电路的系统和方法。自复位电路包括正常模式输入检测电路，其检测数据从输入数据路径到达自复位电路，并响应于此产生正常模式控制信号。自复位电路还包括延迟模式输入检测电路，用于检测来自输入数据路径的数据的到达并响应于此生成延迟模式控制信号。提供了一种切换电路，用于在同时使能延迟模式输入检测电路的同时禁用正常模式输入检测电路。响应于切换电路禁用正常模式输入检测电路，延迟模式控制信号通过延迟门传播，使得所述延迟模式控制信号使所述定时控制路径相对于所述数据输入路径同步。

4. 发明授权

US06229338B1 Method and apparatus for reducing dynamic programmable logic array propagation delay 失效
标题翻译：用于减少动态可编程逻辑阵列传播延迟的方法和装置
公开(公告)号：US06229338B1
公开(公告)日：2001-05-08
申请号：US09498933
申请日：2000-02-04
申请人： Paula Kristine Coulman , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Paula Kristine Coulman , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H01L2500
CPC分类号： H03K19/17704
摘要： A dynamic programmable logic array for implementing control logic in a microprocessor provides higher clock frequencies for data processing systems. The programmable logic array has a reduced propagation delay by virtue of partitioning of the interconnects within the OR plane of the array.
摘要翻译：用于在微处理器中实现控制逻辑的动态可编程逻辑阵列为数据处理系统提供更高的时钟频率。可编程逻辑阵列通过在阵列的OR平面内对互连进行划分而具有减小的传播延迟。

5. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

6. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

7. 发明授权

US06502224B2 Method and apparatus for synthesizing levelized logic 失效
标题翻译：用于合成等级化逻辑的方法和装置
公开(公告)号：US06502224B2
公开(公告)日：2002-12-31
申请号：US09833413
申请日：2001-04-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5054 , Y02T10/82
摘要： A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.
摘要翻译：公开了一种用于合成具有同步输出的逻辑电路的方法和装置。逻辑设计者选择固定数量的电平来合成电路，每个级别实现多个具有相同传播延迟的不同逻辑功能。通过确保每个逻辑功能通过将逻辑功能从电平连接到电平来合成，使得每个信号路径通过每个级别一次且仅一次，从而同步电路输出。

8. 发明授权

US08136061B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US08136061B2
公开(公告)日：2012-03-13
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

9. 发明授权

US06285218B1 Method and apparatus for implementing logic using mask-programmable dynamic logic gates 有权
标题翻译：使用掩码可编程动态逻辑门实现逻辑的方法和装置
公开(公告)号：US06285218B1
公开(公告)日：2001-09-04
申请号：US09567381
申请日：2000-05-10
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
IPC分类号： H03K19094
CPC分类号： H03K19/1736
摘要： A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.
摘要翻译：用于用可编程动态逻辑门实现动态逻辑的方法和装置作为用于高速微处理器设计中的可编程逻辑阵列（PLA）的补充。可选单元的矩阵提供强大的逻辑功能，例如具有最小输入和晶体管的AND-OR门能力。通过使用可编程逻辑阵列和可编程动态门，逻辑块的效率可以大大提高，几乎没有增加电路面积。

10. 发明授权

US07746140B2 Scannable latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

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