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1. 发明申请

US20060291263A1 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US20060291263A1
公开(公告)日：2006-12-28
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：公开了一种存储器系统和方法。在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

2. 发明授权

US07339840B2 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US07339840B2
公开(公告)日：2008-03-04
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C7/00
CPC分类号： G11C5/063
摘要： A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：讨论了存储器系统和方法。存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线路布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

3. 发明申请

US20080222443A1 Controller 审中-公开
标题翻译：控制器
公开(公告)号：US20080222443A1
公开(公告)日：2008-09-11
申请号：US11813952
申请日：2006-01-04
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： G06F1/08
CPC分类号： H03M9/00
摘要： The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).
摘要翻译：本发明涉及一种与时钟信号（clk_hr_i）同步控制的与设备（1）输入的连续时钟信号（clk_hr_i）同步的控制信号（evload_o，odload_o，st_chgclk_o，clk_o，st_chgclk_o，clk_o，stkorfiford_i），其中所述控制器（SE）具有：寄存器装置，用于登记包括多个位位置的至少一个设置信号（st_load_i，st_fiford_i），用于根据一个或多个位位置对时钟信号（clk_hr_i）的边沿进行计数的计数装置设置分别登记在寄存器装置中的信号，以及同步和输出装置，用于使由计数装置计数的值与时钟信号（clk_hr_i）和登记的设置信号同步，并输出至少一个控制信号，其中寄存器装置，计数装置和同步和输出装置被配置和彼此连接，使得输出控制信号取决于相应的有效登记的设定信号占据（占据）多个时间位置中的一个，具有与时钟信号的前沿或后沿同步的半个时钟周期的整数倍的相位差。控制器可以特别用于控制同步并行 - 串行转换器，用于将包括k位位置的并行输入信号转换为与时钟信号（clk_hr_i）同步的串行输出信号序列，该时钟信号（clk_hr_i）被提供在发送电路中接口电路的即将到来的存储器生成（例如DDR4）的非常快的DDR DRAM半导体存储器组件。

4. 发明授权

US07245239B2 Synchronous parallel/serial converter 有权
标题翻译：同步并行/串行转换器
公开(公告)号：US07245239B2
公开(公告)日：2007-07-17
申请号：US11331478
申请日：2006-01-13
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.
摘要翻译：公开了一种同步并行/串行转换器。在一个实施例中，一个同步并行/串行转换器，其接收并行n位输入信号并且包括第一移位寄存器，该第一移位寄存器与具有第一移位寄存器的时钟信号同步地接收具有第一加载信号的输入信号的奇数部分时钟速率是系统时钟的一半时钟速率，并提供串行输出作为第一个一位信号序列; 第二移位寄存器，其以与所述时钟信号同步的第二负载信号接收所述输入信号的偶数部分，并提供串行输出作为第二一比特信号序列; 以及融合单元，其与时钟信号和第二串行1位信号序列同步地与时钟信号同步地熔接第一串行1位信号序列，以形成串行一位输出信号。

5. 发明申请

US20060181444A1 Synchronous parallel/serial converter 有权
标题翻译：同步并行/串行转换器
公开(公告)号：US20060181444A1
公开(公告)日：2006-08-17
申请号：US11331478
申请日：2006-01-13
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.
摘要翻译：公开了一种同步并行/串行转换器。在一个实施例中，一个同步并行/串行转换器，其接收并行n位输入信号并且包括第一移位寄存器，该第一移位寄存器与具有第一移位寄存器的时钟信号同步地接收具有第一加载信号的输入信号的奇数部分时钟速率是系统时钟的一半时钟速率，并提供串行输出作为第一个一位信号序列; 第二移位寄存器，其以与所述时钟信号同步的第二负载信号接收所述输入信号的偶数部分，并提供串行输出作为第二一比特信号序列; 以及融合单元，其与时钟信号和第二串行1位信号序列同步地与时钟信号同步地熔接第一串行1位信号序列，以形成串行一位输出信号。

6. 发明申请

US20070058409A1 Semiconductor memory arrangement with branched control and address bus 失效
标题翻译：具有分支控制和地址总线的半导体存储器
公开(公告)号：US20070058409A1
公开(公告)日：2007-03-15
申请号：US11226448
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Christian Weiss , Ralf Schledz , Johannes Stecker
发明人： Hermann Ruckerbauer , Christian Weiss , Ralf Schledz , Johannes Stecker
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片的数据存储器系统中操作的半导体存储器装置包括用于控制至少一个半导体存储器芯片的存储器控制器和用于控制的至少一个单向信号线总线，与存储器控制器连接的地址信号并至少分支一次。所述至少一次分支总线将至少一个半导体存储器芯片与存储器控制器直接连接并将半导体存储器芯片彼此连接。

7. 发明申请

US20070058408A1 Semiconductor memory array with serial control/address bus 有权
标题翻译：具有串行控制/地址总线的半导体存储器阵列
公开(公告)号：US20070058408A1
公开(公告)日：2007-03-15
申请号：US11226447
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
发明人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。

8. 发明授权

US07411843B2 Semiconductor memory arrangement with branched control and address bus 失效
标题翻译：具有分支控制和地址总线的半导体存储器
公开(公告)号：US07411843B2
公开(公告)日：2008-08-12
申请号：US11226448
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Christian Weiss , Ralf Schledz , Johannes Stecker
发明人： Hermann Ruckerbauer , Christian Weiss , Ralf Schledz , Johannes Stecker
IPC分类号： G11C7/00
CPC分类号： G11C5/063
摘要： A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片的数据存储器系统中操作的半导体存储器装置包括用于控制至少一个半导体存储器芯片的存储器控制器和用于控制的至少一个单向信号线总线，与存储器控制器连接的地址信号并至少分支一次。所述至少一次分支总线将至少一个半导体存储器芯片与存储器控制器直接连接并将半导体存储器芯片彼此连接。

9. 发明授权

US07397684B2 Semiconductor memory array with serial control/address bus 有权
标题翻译：具有串行控制/地址总线的半导体存储器阵列
公开(公告)号：US07397684B2
公开(公告)日：2008-07-08
申请号：US11226447
申请日：2005-09-15
申请人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
发明人： Hermann Ruckerbauer , Ralf Schledz , Johannes Stecker , Dominique Savignac , Georg Braun
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G06F13/1668
摘要： A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
摘要翻译：一种用于在具有用于存储用户数据的至少一个半导体存储器芯片和用于控制至少一个半导体存储器芯片的一个存储器控制器的数据存储系统中操作的半导体存储器阵列包括至少一个用于控制的单向串行信号线总线以及与存储器控制器连接的地址信号，将至少一个半导体存储器芯片与存储器控制器直接连接，并且通过1点到1点连接彼此串联连接半导体存储器芯片。

10. 发明授权

US08125812B2 Method and device for transmitting outgoing useful signals and an outgoing clock signal 有权
标题翻译：用于发送输出有用信号和输出时钟信号的方法和装置
公开(公告)号：US08125812B2
公开(公告)日：2012-02-28
申请号：US12058899
申请日：2008-03-31
申请人： Martin Streibl , Peter Gregorius , Ralf Schledz
发明人： Martin Streibl , Peter Gregorius , Ralf Schledz
IPC分类号： G11C5/02
CPC分类号： G11C7/22 , G06F1/10 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.
摘要翻译：用于发送输出有用信号和输出时钟信号的方法和装置。有用的信号和时钟信号从发射机经由第一线对和第二线对发射到接收机。第一有用信号以第一线对的电位之间的调制差的形式发送。第二有用信号以第二线对的电位之间的调制差的形式传输。时钟信号以第一线对的电位的平均值与第二线对的电位的平均值之间的调制差的形式发送。

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