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1. 发明申请

US20080222443A1 Controller 审中-公开
标题翻译：控制器
公开(公告)号：US20080222443A1
公开(公告)日：2008-09-11
申请号：US11813952
申请日：2006-01-04
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： G06F1/08
CPC分类号： H03M9/00
摘要： The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set signal, occupies (occupy) one of a plurality of temporal positions with a respective phase difference of an integral multiple of half a clock cycle synchronously with the leading or trailing edge of the clock signal. The controller can be applied in particular for controlling the synchronous parallel-serial converter for converting a parallel input signal comprising k bit positions into a serial output signal sequence synchronously with the clock signal (clk_hr_i), which converter is provided in a transmitting circuit in the interface circuit of a very fast DDR DRAM semiconductor memory component of the coming memory generation (e.g. DDR4).
摘要翻译：本发明涉及一种与时钟信号（clk_hr_i）同步控制的与设备（1）输入的连续时钟信号（clk_hr_i）同步的控制信号（evload_o，odload_o，st_chgclk_o，clk_o，st_chgclk_o，clk_o，stkorfiford_i），其中所述控制器（SE）具有：寄存器装置，用于登记包括多个位位置的至少一个设置信号（st_load_i，st_fiford_i），用于根据一个或多个位位置对时钟信号（clk_hr_i）的边沿进行计数的计数装置设置分别登记在寄存器装置中的信号，以及同步和输出装置，用于使由计数装置计数的值与时钟信号（clk_hr_i）和登记的设置信号同步，并输出至少一个控制信号，其中寄存器装置，计数装置和同步和输出装置被配置和彼此连接，使得输出控制信号取决于相应的有效登记的设定信号占据（占据）多个时间位置中的一个，具有与时钟信号的前沿或后沿同步的半个时钟周期的整数倍的相位差。控制器可以特别用于控制同步并行 - 串行转换器，用于将包括k位位置的并行输入信号转换为与时钟信号（clk_hr_i）同步的串行输出信号序列，该时钟信号（clk_hr_i）被提供在发送电路中接口电路的即将到来的存储器生成（例如DDR4）的非常快的DDR DRAM半导体存储器组件。

2. 发明授权

US07339840B2 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US07339840B2
公开(公告)日：2008-03-04
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C7/00
CPC分类号： G11C5/063
摘要： A memory system and method is discussed. The memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：讨论了存储器系统和方法。存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线路布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

3. 发明申请

US20060291263A1 Memory system and method of accessing memory chips of a memory system 失效
标题翻译：存储器系统和访问存储器系统的存储器芯片的方法
公开(公告)号：US20060291263A1
公开(公告)日：2006-12-28
申请号：US11128789
申请日：2005-05-13
申请人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
发明人： Paul Wallner , Ralf Schledz , Peter Gregorius , Hermann Ruckerbauer
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.
摘要翻译：公开了一种存储器系统和方法。在一个实施例中，存储器系统包括存储器控制器和至少一个存储器模块，其中一定数量的半导体存储器芯片和连接线被布置在分别指定的拓扑中。连接线包括形成传输通道的第一连接线，用于基于协议的数据传输和命令信号流从存储器控制器分别存储到存储器模块上的存储器芯片和存储器控制器中的至少一个。将第二连接线从存储器控制器直接路由到存储器模块上的至少一个存储器芯片，用于将选择信息与数据和命令信号流分离地传送到至少一个存储器芯片。

4. 发明授权

US07245239B2 Synchronous parallel/serial converter 有权
标题翻译：同步并行/串行转换器
公开(公告)号：US07245239B2
公开(公告)日：2007-07-17
申请号：US11331478
申请日：2006-01-13
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.
摘要翻译：公开了一种同步并行/串行转换器。在一个实施例中，一个同步并行/串行转换器，其接收并行n位输入信号并且包括第一移位寄存器，该第一移位寄存器与具有第一移位寄存器的时钟信号同步地接收具有第一加载信号的输入信号的奇数部分时钟速率是系统时钟的一半时钟速率，并提供串行输出作为第一个一位信号序列; 第二移位寄存器，其以与所述时钟信号同步的第二负载信号接收所述输入信号的偶数部分，并提供串行输出作为第二一比特信号序列; 以及融合单元，其与时钟信号和第二串行1位信号序列同步地与时钟信号同步地熔接第一串行1位信号序列，以形成串行一位输出信号。

5. 发明申请

US20060181444A1 Synchronous parallel/serial converter 有权
标题翻译：同步并行/串行转换器
公开(公告)号：US20060181444A1
公开(公告)日：2006-08-17
申请号：US11331478
申请日：2006-01-13
申请人： Paul Wallner , Peter Gregorius , Ralf Schledz
发明人： Paul Wallner , Peter Gregorius , Ralf Schledz
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , G11C7/1051 , G11C7/1066 , G11C2207/107
摘要： A synchronous parallel/serial converter is disclosed. In one embodiment, the a synchronous parallel/serial converter that receives a parallel n-bit input signal and comprising a first shift register that receives an odd-numbered part of the input signal with a first load signal in synchronism with a clock signal having a clock rate half the clock rate of a system clock, and provides a serial output as a first one-bit signal sequence; a second shift register that receives an even-numbered part of the input signal with a second load signal synchronism with the clock signal and provides a serial output as a second one-bit signal sequence; and a fusion unit that fuses the first serial one-bit signal sequence synchronously with the clock signal and the second serial one-bit signal sequence in synchronism the clock signal to form a serial one-bit output signal.
摘要翻译：公开了一种同步并行/串行转换器。在一个实施例中，一个同步并行/串行转换器，其接收并行n位输入信号并且包括第一移位寄存器，该第一移位寄存器与具有第一移位寄存器的时钟信号同步地接收具有第一加载信号的输入信号的奇数部分时钟速率是系统时钟的一半时钟速率，并提供串行输出作为第一个一位信号序列; 第二移位寄存器，其以与所述时钟信号同步的第二负载信号接收所述输入信号的偶数部分，并提供串行输出作为第二一比特信号序列; 以及融合单元，其与时钟信号和第二串行1位信号序列同步地与时钟信号同步地熔接第一串行1位信号序列，以形成串行一位输出信号。

6. 发明授权

US08125812B2 Method and device for transmitting outgoing useful signals and an outgoing clock signal 有权
标题翻译：用于发送输出有用信号和输出时钟信号的方法和装置
公开(公告)号：US08125812B2
公开(公告)日：2012-02-28
申请号：US12058899
申请日：2008-03-31
申请人： Martin Streibl , Peter Gregorius , Ralf Schledz
发明人： Martin Streibl , Peter Gregorius , Ralf Schledz
IPC分类号： G11C5/02
CPC分类号： G11C7/22 , G06F1/10 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/222
摘要： Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.
摘要翻译：用于发送输出有用信号和输出时钟信号的方法和装置。有用的信号和时钟信号从发射机经由第一线对和第二线对发射到接收机。第一有用信号以第一线对的电位之间的调制差的形式发送。第二有用信号以第二线对的电位之间的调制差的形式传输。时钟信号以第一线对的电位的平均值与第二线对的电位的平均值之间的调制差的形式发送。

7. 发明授权

US07461186B2 Data handover unit for transferring data between different clock domains by parallelly reading out data bits from a plurality of storage elements 有权
标题翻译：数据切换单元，用于通过从多个存储元件并行读出数据位，在不同的时钟域之间传送数据
公开(公告)号：US07461186B2
公开(公告)日：2008-12-02
申请号：US11346993
申请日：2006-02-03
申请人： Martin Streibl , Peter Gregorius , Ralf Schledz , Thomas Rickes , Zheng Gu
发明人： Martin Streibl , Peter Gregorius , Ralf Schledz , Thomas Rickes , Zheng Gu
IPC分类号： G06F13/38 , G06F11/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093
摘要： The invention provides a data handover unit for transferring data from a furst clock domain to a second clock domain, comprising: a first clock unit operable to supply a first clock signal; a selector stage operable to sample an incoming data stream with respect to the first clock signal; a second clock unit operable to supply a second clock signal; a storage unit coupled with the selector stage, wherein the storage unit has a first plurality of storage elements each of which is operable to store one bit of data of the sampled data stream, an output unit for parallelly reading out a fram of data from a second plurality of storage elements included in the first plurality of storage elements with respect to the second clock signal, wherein the selector stage is further operable to successively write the data bits of the sampled data stream into the first plurality of storage elements and to store the respective data bits of the sampled data stream in the respective storage elements until they were read out by the output unit.
摘要翻译：本发明提供一种用于将数据从第一时钟域传送到第二时钟域的数据切换单元，包括：第一时钟单元，用于提供第一时钟信号; 选择器级，可操作以相对于所述第一时钟信号对输入数据流进行采样; 第二时钟单元，用于提供第二时钟信号; 与所述选择器级耦合的存储单元，其中所述存储单元具有第一多个存储元件，每个存储元件可操作以存储所述采样数据流的一位数据;输出单元，用于从第二多个存储元件相对于第二时钟信号包括在第一多个存储元件中，其中选择器级还可操作以将采样数据流的数据位连续地写入第一多个存储元件并存储相应的存储元件中的采样数据流的相应数据位直到它们被输出单元读出。

8. 发明申请

US20070258552A1 DATA RECEIVER WITH CLOCK RECOVERY CIRCUIT 有权
标题翻译：具有时钟恢复电路的数据接收器
公开(公告)号：US20070258552A1
公开(公告)日：2007-11-08
申请号：US11742577
申请日：2007-04-30
申请人： Martin Streibl , Peter Gregorius , Thomas Rickes , Ralf Schledz
发明人： Martin Streibl , Peter Gregorius , Thomas Rickes , Ralf Schledz
IPC分类号： H04L7/00
CPC分类号： H04L7/0054 , G11C7/1078 , G11C7/1084 , H03L7/08 , H04L7/007
摘要： A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.
摘要翻译：数据接收机具有连接到数据信号输入端并被配置为采样数据信号振幅并将采样数据信号振幅放大到预定值的采样单元，采样时钟发生器单元连接到采样单元并被配置为预先确定采样时钟对于采样单元，评估单元连接到采样单元并且被配置为确定采样单元需要的持续时间以将采样的数据信号幅度放大到预定值并评估所确定的持续时间，以及控制单元评估单元和采样时钟发生器，并且被配置为基于由评估单元确定的持续时间的评估来定义采样时钟。

9. 发明授权

US07817766B2 Apparatus and method for avoiding steady-state oscillations in the generation of clock signals 有权
标题翻译：用于在时钟信号的产生中避免稳态振荡的装置和方法
公开(公告)号：US07817766B2
公开(公告)日：2010-10-19
申请号：US11554554
申请日：2006-10-30
申请人： Peter Gregorius , Thomas Rickes , Ralf Schledz , Martin Streibl
发明人： Peter Gregorius , Thomas Rickes , Ralf Schledz , Martin Streibl
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/0805
摘要： A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.
摘要翻译：数字控制回路和时钟生成方法。控制回路包括至少一个相位检测器，被配置为检测反馈信号相对于参考时钟信号的相移，并且基于检测到的相移输出校正信号。至少一个控制环路滤波器被配置为基于校正信号输出第一控制信号和第二控制信号，第一控制信号基本上与第二控制信号相同，除了在第二控制信号中振荡被抑制控制信号。至少一个第一相位发生器被配置为基于第一控制信号和第一相位参考信号来输出第一时钟信号，其中第一时钟信号至少部分地作为反馈信号发送到相位检测器。至少一个第二相位发生器接收第二控制信号和第一相位参考信号，其中第二相位发生器在功能上基本上与第一相位发生器相同，并且被配置为基于第二控制信号输出第二时钟信号和第一相位参考信号。

10. 发明申请

US20070133730A1 APPARATUS AND METHOD FOR AVOIDING STEADY-STATE OSCILLATIONS IN THE GENERATION OF CLOCK SIGNALS 有权
标题翻译：在时钟信号发生中避免稳态振荡的装置和方法
公开(公告)号：US20070133730A1
公开(公告)日：2007-06-14
申请号：US11554554
申请日：2006-10-30
申请人： Peter Gregorius , Thomas Rickes , Ralf Schledz , Martin Streibl
发明人： Peter Gregorius , Thomas Rickes , Ralf Schledz , Martin Streibl
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03L7/0805
摘要： A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.
摘要翻译：数字控制回路和时钟生成方法。控制回路包括至少一个相位检测器，被配置为检测反馈信号相对于参考时钟信号的相移，并且基于检测到的相移输出校正信号。至少一个控制环路滤波器被配置为基于校正信号输出第一控制信号和第二控制信号，第一控制信号基本上与第二控制信号相同，除了在第二控制信号中振荡被抑制控制信号。至少一个第一相位发生器被配置为基于第一控制信号和第一相位参考信号来输出第一时钟信号，其中第一时钟信号至少部分地作为反馈信号发送到相位检测器。至少一个第二相位发生器接收第二控制信号和第一相位参考信号，其中第二相位发生器在功能上基本上与第一相位发生器相同，并且被配置为基于第二控制信号输出第二时钟信号和第一相位参考信号。

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