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1. 发明授权

US06807125B2 Circuit and method for reading data transfers that are sent with a source synchronous clock signal 失效
标题翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法
公开(公告)号：US06807125B2
公开(公告)日：2004-10-19
申请号：US10225871
申请日：2002-08-22
申请人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
发明人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
IPC分类号： G11C1100
CPC分类号： G11C7/106 , G11C7/1045 , G11C7/1051 , G11C7/1066
摘要： A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
摘要翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法。该电路具有数据输入端，用于接收承载传送数据的数据信号，用于接收同步时钟信号的时钟输入端和连接到时钟输入端的延迟电路，用于产生从所述同步时钟信号延迟预定时间的延迟时钟信号期。电路还包括连接到数据输入端的流水线，用于响应于所述延迟的时钟信号对数据输入上的数据进行采样，从而延伸输入数据的采样。

2. 发明授权

US07895374B2 Dynamic segment sparing and repair in a memory system 失效
标题翻译：内存系统中的动态段保存和修复
公开(公告)号：US07895374B2
公开(公告)日：2011-02-22
申请号：US12165809
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

3. 发明申请

US20100005345A1 BIT SHADOWING IN A MEMORY SYSTEM 失效
标题翻译：记忆系统中的位冲突
公开(公告)号：US20100005345A1
公开(公告)日：2010-01-07
申请号：US12165799
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G06F11/073 , G06F11/076 , G06F11/1004 , G06F11/2007 , G11C5/04 , G11C29/02 , G11C29/022
摘要： A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：提供了一种用于存储器系统中的位阴影的通信接口设备，系统，方法和设计结构。通信接口设备包括用于选择驱动器位位置作为阴影驱动器值的阴影选择逻辑，以及线驱动器，以在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。通信接口设备还包括阴影比较逻辑，以将所选择的接收值与来自总线的阴影接收值进行比较，并且识别响应于比较不匹配的错误比较，以及阴影计数器来计数相对于总线的误比率错误率在一段时间内。响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

4. 发明申请

US20090094476A1 DERIVING CLOCKS IN A MEMORY SYSTEM 失效
标题翻译：在记忆系统中传送时钟
公开(公告)号：US20090094476A1
公开(公告)日：2009-04-09
申请号：US12332396
申请日：2008-12-11
申请人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
发明人： Frank D. Ferraiolo , Kevin C. Gower , Martin L. Schmatz
IPC分类号： G06F1/00 , G06F1/06
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译：提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。该方法包括在集线器设备处接收参考振荡器时钟。集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。以基准时钟频率工作的基本时钟从参考振荡器时钟导出。通过将基本时钟乘以存储器乘法器导出存储器接口时钟。控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。

5. 发明授权

US08139430B2 Power-on initialization and test for a cascade interconnect memory system 失效
标题翻译：级联互连存储器系统的上电初始化和测试
公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G11C7/10 , G11C7/18
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译：用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。该接口可在SBC模式和高速模式下工作。存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。

6. 发明授权

US08082475B2 Enhanced microprocessor interconnect with bit shadowing 有权
标题翻译：增强的微处理器互连与位阴影
公开(公告)号：US08082475B2
公开(公告)日：2011-12-20
申请号：US12165848
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F11/14 , G06F11/30
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译：阴影选择逻辑用于选择驱动程序位位置作为阴影驱动程序值，线路驱动程序可以在总线的单独链路段上传输所选驱动程序位位置和阴影驱动程序值的数据。此外，阴影比较逻辑用于将选定的接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线错误率的速率经过一段时间。响应于在总线错误率的预定义阈值内的错误比较的速率来识别有缺陷的链路段。

7. 发明申请

US20100005202A1 DYNAMIC SEGMENT SPARING AND REPAIR IN A MEMORY SYSTEM 失效
标题翻译：动态部分在记忆系统中的分配和修复
公开(公告)号：US20100005202A1
公开(公告)日：2010-01-07
申请号：US12165809
申请日：2008-07-01
申请人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
发明人： Frank D. Ferraiolo , Ravi K. Arimilli , Daniel M. Dreps , Kevin C. Gower , Robert J. Reese
IPC分类号： G06F3/00
CPC分类号： G06F13/4243 , G06F11/2007 , G06F11/2017 , Y02D10/14 , Y02D10/151
摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.
摘要翻译：用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段。

8. 发明授权

US07551468B2 276-pin buffered memory module with enhanced fault tolerance 失效
标题翻译： 276引脚缓冲存储器模块，具有增强的容错能力
公开(公告)号：US07551468B2
公开(公告)日：2009-06-23
申请号：US12060992
申请日：2008-04-02
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
IPC分类号： G11C5/06 , G11C5/02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译：双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡片包括至少276个配置在其上的针脚。

9. 发明申请

US20080177942A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE 失效
公开(公告)号：US20080177942A1
公开(公告)日：2008-07-24
申请号：US12060998
申请日：2008-04-02
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
IPC分类号： G06F12/00
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.

10. 发明授权

US07305574B2 System, method and storage medium for bus calibration in a memory subsystem 失效
标题翻译：用于内存子系统总线校准的系统，方法和存储介质
公开(公告)号：US07305574B2
公开(公告)日：2007-12-04
申请号：US10977048
申请日：2004-10-29
申请人： Frank D. Ferraiolo , Kevin C. Gower
发明人： Frank D. Ferraiolo , Kevin C. Gower
IPC分类号： G11C7/10 , G06F1/00
CPC分类号： G06F13/4239
摘要： A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.
摘要翻译：具有一个或多个存储器模块的级联互连系统，存储器控制器和利用定期重新校准的存储器总线。存储器模块和存储器控制器通过存储器总线通过分组化的多传输接口直接互连，并提供用于定期重新校准的加扰数据。

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