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1. 发明授权

US06300666B1 Method for forming a frontside contact to the silicon substrate of a SOI wafer in the presence of planarized contact dielectrics 失效
标题翻译：在存在平坦化的接触电介质的情况下，在SOI晶片的硅衬底上形成前端接触的方法
公开(公告)号：US06300666B1
公开(公告)日：2001-10-09
申请号：US09163687
申请日：1998-09-30
申请人： Paul S. Fechner , Gregory D. Dougal , Keith W. Golke
发明人： Paul S. Fechner , Gregory D. Dougal , Keith W. Golke
IPC分类号： H01L2900
CPC分类号： H01L27/0218 , H01L21/76895 , H01L29/78636 , H01L29/78639
摘要： A method for forming a frontside substrate contact on a Silicon-On-Insulator wafer in the presence of planarized contact dielectric is described. The method offers the improvement of reducing the etch selectivity requirements while allowing simultaneous etching and metallization of gate, source, drain and substrate contacts.
摘要翻译：描述了在存在平坦化接触电介质的情况下在绝缘体上硅晶片上形成前面衬底接触的方法。该方法提供了降低蚀刻选择性要求的改进，同时允许栅极，源极，漏极和衬底触点的同时蚀刻和金属化。

2. 发明授权

US06180984B2 Integrated circuit impedance device and method of manufacture therefor 失效
标题翻译：集成电路阻抗装置及其制造方法
公开(公告)号：US06180984B2
公开(公告)日：2001-01-30
申请号：US09219804
申请日：1998-12-23
申请人： Keith W. Golke , Paul S. Fechner
发明人： Keith W. Golke , Paul S. Fechner
IPC分类号： H01L2910
CPC分类号： H01L21/84 , H01L27/1203
摘要： A multi-purpose device that can serve as either a resistor, MOSFET or JFET is disclosed. The resistor is formed by selecting a first metal interconnect configuration, the MOSFET is formed by selecting a second metal interconnect configuration, and the JFET is formed by selecting a third metal interconnect configuration. Because of the dual transistor/resistor nature of this device, the density of a typical gate array that uses resistors may be increased. In addition, and because no special processing is typically required, the device may be desirable for use in other types of structures such as standard cells and custom logic.
摘要翻译：公开了可以用作电阻器，MOSFET或JFET的多用途器件。通过选择第一金属互连配置来形成电阻器，通过选择第二金属互连配置形成MOSFET，并且通过选择第三金属互连配置来形成JFET。由于该器件的双晶体管/电阻器性质，可能会增加使用电阻器的典型栅极阵列的密度。此外，由于通常不需要特殊处理，所以该装置可能需要用于其他类型的结构，例如标准单元和定制逻辑。

3. 发明授权

US6058041A SEU hardening circuit 有权
标题翻译： SEU硬化电路
公开(公告)号：US6058041A
公开(公告)日：2000-05-02
申请号：US219807
申请日：1998-12-23
申请人： Keith W. Golke , Paul S. Fechner
发明人： Keith W. Golke , Paul S. Fechner
IPC分类号： H03K19/0944 , G11C5/00 , G11C11/412 , G11C11/00
CPC分类号： G11C5/005 , G11C11/4125
摘要： A SEU hardening circuit for use with a data storage circuit is described. The SEU hardening circuit may use a transmission gate to provide full rail drive during a write operation. The SEU hardening circuit may also be configured so that the transistors of the SEU hardening circuit are not susceptible to parasitic bipolar turn-on particularly during a radiation event, which can increase the SEU protection provided by the circuit.
摘要翻译：描述了与数据存储电路一起使用的SEU硬化电路。 SEU硬化电路可以在写入操作期间使用传输门来提供完整的轨道驱动。 SEU硬化电路也可以被配置为使得SEU硬化电路的晶体管不易受寄生双极导通，特别是在辐射事件期间，这可能增加由电路提供的SEU保护。

4. 发明授权

US5631863A Random access memory cell resistant to radiation induced upsets 失效
标题翻译：随机存取存储单元抵抗辐射诱发的不适
公开(公告)号：US5631863A
公开(公告)日：1997-05-20
申请号：US587065
申请日：1996-01-16
申请人： Paul S. Fechner , Gregor D. Dougal , Keith W. Golke
发明人： Paul S. Fechner , Gregor D. Dougal , Keith W. Golke
IPC分类号： G11C11/412
CPC分类号： G11C11/4125 , Y10S257/903 , Y10S257/904
摘要： A radiation resistant random access memory cell which has a coupling circuit between a storage node of a first CMOS pair and a gate node of a second CMOS pair. The coupling circuit is controlled by a word line and provides a first resistive element between the storage node and the body of the coupling circuit and a second resistive element between the gate node and the body of the coupling circuit.
摘要翻译：一种耐辐射随机存取存储单元，其具有在第一CMOS对的存储节点和第二CMOS对的栅极节点之间的耦合电路。耦合电路由字线控制，并且在存储节点和耦合电路的主体之间提供第一电阻元件，并且在栅极节点和耦合电路的主体之间提供第二电阻元件。

5. 发明申请

US20120228513A1 NEUTRON DETECTOR CELL EFFICIENCY 有权
标题翻译：中子检测器细胞效率
公开(公告)号：US20120228513A1
公开(公告)日：2012-09-13
申请号：US13424269
申请日：2012-03-19
申请人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
发明人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
IPC分类号： G01T1/24
CPC分类号： G01T3/08 , G11C5/005
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译：阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。

6. 发明授权

US07732287B2 Method of forming a body-tie 有权
标题翻译：形成身体的方法
公开(公告)号：US07732287B2
公开(公告)日：2010-06-08
申请号：US11415703
申请日：2006-05-02
申请人： Paul S. Fechner , Gordon A. Shaw , Eric E. Vogt
发明人： Paul S. Fechner , Gordon A. Shaw , Eric E. Vogt
IPC分类号： H01L21/336
CPC分类号： H01L29/78615 , H01L29/66772
摘要： A method of forming a body-tie. The method includes forming the body-tie during an STI scheme of an SOI process. During the STI scheme, a first trench is formed. The first trench stops before a buried oxide layer of the SOI substrate. The first trench may determine a height of body tie that is shared between at least two FETs. A second trench may also be formed within the first trench. The second trench stops in the SOI substrate. The second trench defines the location and shape of a body-tie. Once the location and shape of the body-tie are defined, an oxide is deposited above the body-tie. The deposited oxide prevents certain implants from entering the body tie. By preventing these implants, a source and a drain implant may be self-aligned to the source and drain areas without requiring the use of the photoresist mask to shield the body tie regions from the source and drain implant.
摘要翻译：一种形成身体的方法。该方法包括在SOI工艺的STI方案期间形成体系。在STI方案中，形成第一沟槽。第一沟槽在SOI衬底的掩埋氧化物层之前停止。第一沟槽可以确定在至少两个FET之间共享的身体连接的高度。也可以在第一沟槽内形成第二沟槽。第二沟槽在SOI衬底中停止。第二个沟槽定义了一个领带的位置和形状。一旦定义了身体领带的位置和形状，就会在身体绑带上方沉积氧化物。沉积的氧化物防止某些植入物进入身体束带。通过防止这些植入物，源极和漏极注入可以与源极和漏极区域自对准，而不需要使用光致抗蚀剂掩模来屏蔽源极和漏极植入物的主体连接区域。

7. 发明申请

US20090065866A1 Non-Planar Silicon-On-Insulator Device that Includes an "Area-Efficient" Body Tie 有权
标题翻译：包含“区域高效”身体领带的非平面矽绝缘体设备
公开(公告)号：US20090065866A1
公开(公告)日：2009-03-12
申请号：US11853611
申请日：2007-09-11
申请人： Bradley J. Larsen , Michael S. Liu , Paul S. Fechner
发明人： Bradley J. Larsen , Michael S. Liu , Paul S. Fechner
IPC分类号： H01L29/786
CPC分类号： H01L29/7853 , H01L29/66795 , H01L29/78615
摘要： Non-planar SOI devices that include an “area-efficient” body tie are disclosed. The device includes a bulk substrate, an insulator layer formed on a surface of the bulk substrate, and a silicon body formed on a surface of the insulator layer. The silicon body preferably includes (i) a non-planar channel connecting a source region and a drain region, and (ii) a body tie that is adjacent to the channel and couples the channel to a voltage potential. The device further includes a gate dielectric formed on the channel and a gate material formed on the gate dielectric.
摘要翻译：公开了包括“面积效率”的身体搭接的非平面SOI器件。该器件包括体基片，形成在本体基片的表面上的绝缘体层，以及形成在绝缘体层的表面上的硅体。硅体优选地包括（i）连接源极区域和漏极区域的非平面沟道，以及（ii）与沟道相邻并且将沟道耦合到电压电位的主体连接。该器件还包括形成在沟道上的栅极电介质和形成在栅极电介质上的栅极材料。

8. 发明授权

US06433983B1 High performance output buffer with ESD protection 有权
标题翻译：具有ESD保护功能的高性能输出缓冲器
公开(公告)号：US06433983B1
公开(公告)日：2002-08-13
申请号：US09449312
申请日：1999-11-24
申请人： Paul S. Fechner
发明人： Paul S. Fechner
IPC分类号： H02G900
CPC分类号： H01L27/11898 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An output buffer with built-in ESD protection is disclosed. The built-in ESD protection is preferably formed using transistors from the sea-of-transistors or sea-of-gates region of the integrated circuit, which may eliminate the need for dedicated ESD devices, and in particular, dedicated ESD devices that are pre-fabricated into the under-layers in and around the perimeter of the integrated circuit.
摘要翻译：公开了具有内置ESD保护的输出缓冲器。内置的ESD保护优选使用来自集成电路的晶体管或晶体管的区域的晶体管形成，这可以消除对专用ESD器件的需要，特别是预先设置的专用ESD器件 - 集成到集成电路周边和周围的下层。

9. 发明授权

US08742831B2 Method for digital programmable optimization of mixed-signal circuits 有权
标题翻译：混合信号电路数字可编程优化方法
公开(公告)号：US08742831B2
公开(公告)日：2014-06-03
申请号：US12390792
申请日：2009-02-23
申请人： Paul S. Fechner
发明人： Paul S. Fechner
IPC分类号： H03K3/01 , G05F1/46
CPC分类号： G05F1/46 , H03F1/301 , H03F1/304 , H03F2200/366
摘要： A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements.
摘要翻译：提供了一种用于混合信号电路的数字可编程优化的方法。该方法包括将混合信号电路的一个或多个晶体管器件分成一个或多个晶体管段，其中每个晶体管段包括主体偏置端子。每个主体连接偏置端子通过将每个主体连接偏置端子与混合信号电路中的一个或多个偏置节点进行信号通信，或者通过将每个主体连接偏置端子与信号通信置于信号通信中来耦合至少一个电压偏置非精密偏置电压源。每个身体接合终端还被布置成与一个或多个数字可编程存储元件中的单独的一个信号通信。

10. 发明授权

US08399845B2 Neutron detector cell efficiency 有权
标题翻译：中子检测器电池效率
公开(公告)号：US08399845B2
公开(公告)日：2013-03-19
申请号：US13424269
申请日：2012-03-19
申请人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
发明人： Paul S. Fechner , David O. Erstad , Todd A. Randazzo , Bradley J. Larsen
IPC分类号： G01T3/00
CPC分类号： G01T3/08 , G11C5/005
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译：阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。

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