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1. 发明授权

US07190979B1 Battery economizing in a communications system 有权
标题翻译：电池节省通信系统
公开(公告)号：US07190979B1
公开(公告)日：2007-03-13
申请号：US09653782
申请日：2000-09-01
申请人： Paul R. Marshall , David K. Roberts , Richard C. Burbidge
发明人： Paul R. Marshall , David K. Roberts , Richard C. Burbidge
IPC分类号： H04B1/38
CPC分类号： H04L1/0045 , H04W52/0229 , H04W52/0241 , H04W52/0245 , Y02D70/166
摘要： In communications systems such as telemetry systems in which a receiver (34) is periodically energised to receive transmissions from a central station, the receiver includes a power control means (12) for controlling the energisation of the receiver, a circuit (48) for detecting the presence of a carrier, which circuit (48) causes the power control means to de-energise the receiver (34) in the event of carrier not being detected, and a signal quality measuring stage (50) for determining if the demodulated signal is decodable, the stage (50) causing the power control means to de-energise the receiver (34) in the event of the signal quality not being acceptable.
摘要翻译：在诸如遥测系统的通信系统中，接收器（34）周期性地被激励以接收来自中心站的传输，所述接收机包括用于控制接收机通电的功率控制装置（12），用于检测的电路（48）载波的存在，该电路（48）使得功率控制装置在载波未被检测的情况下使接收机（34）断电;以及信号质量测量级（50），用于确定解调信号是否为可解码，在信号质量不可接受的情况下，使得功率控制装置使接收器（34）断电的级（50）。

2. 发明授权

US06570948B1 Phase locked loop frequency generating circuit and a receiver using the circuit 失效
标题翻译：锁相环频率发生电路和使用该电路的接收机
公开(公告)号：US06570948B1
公开(公告)日：2003-05-27
申请号：US09663635
申请日：2000-09-18
申请人： Paul R. Marshall
发明人： Paul R. Marshall
IPC分类号： H03D324
CPC分类号： H03L7/0802 , H03L7/23
摘要： A frequency generating circuit comprises a first, fine PLL frequency synthesiser circuit (FS2) which consumes a low current and is slow to settle, a second, coarse PLL frequency synthesiser circuit (FS1) which consumes a high current and is fast to settle, and a signal combining circuit (36) for additively combining the outputs of the first and second frequency synthesiser circuits to provide a final output frequency. The first frequency synthesiser circuit is energised sufficiently in advance of the second frequency synthesiser circuit that both achieve lock substantially simultaneously. The overall current consumed is less than would be consumed if a single PLL frequency synthesiser is used to generate the final frequency.
摘要翻译：频率发生电路包括消耗低电流且缓慢稳定的第一精细PLL频率合成器电路（FS2），消耗高电流且快速稳定的第二粗略PLL频率合成器电路（FS1），以及信号组合电路（36），用于相加地组合第一和第二频率合成器电路的输出以提供最终的输出频率。第一频率合成器电路在第二频率合成器电路之前被充分充电，两者都基本同时实现锁定。如果使用单个PLL频率合成器来产生最终频率，则消耗的总电流小于消耗的电流。

3. 发明授权

US07157979B2 Phase-lock loops 有权
标题翻译：锁相环
公开(公告)号：US07157979B2
公开(公告)日：2007-01-02
申请号：US10526197
申请日：2003-08-22
申请人： Adrian G. Spencer , Paul R. Marshall
发明人： Adrian G. Spencer , Paul R. Marshall
IPC分类号： H03L7/00
CPC分类号： H03C3/0991 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03L7/0898 , H03L7/093 , H03L7/197 , H03L7/1976
摘要： A phase lock loop comprises a variable frequency oscillator (20), a divider (30), a phase comparator (40), a gain control stage (240), and a loop filter (50). The frequency response of the loop is measured by superimposing a modulation at a number of different rates on the error signal generated by the phase comparator, and by measuring for each modulation rate the peak-to-peak variation of the loop control signal controlling the oscillator frequency. If, due to errors in component values, the frequency response deviates from its desired value, the loop gain is adjusted to bring the frequency response close to its desired value.
摘要翻译：锁相环包括可变频率振荡器（20），分频器（30），相位比较器（40），增益控制级（240）和环路滤波器（50）。环路的频率响应是通过将由多个不同速率的调制叠加在由相位比较器产生的误差信号上，并通过测量每个调制速率来测量控制振荡器的环路控制信号的峰 - 峰变化频率。如果由于组件值的错误，频率响应偏离其所需值，则调整环路增益以使频率响应接近其所需值。

4. 发明授权

US06795517B1 Low power phase locked loop frequency synthesizer 有权
标题翻译：低功率锁相环频率合成器
公开(公告)号：US06795517B1
公开(公告)日：2004-09-21
申请号：US09663674
申请日：2000-09-18
申请人： Paul R. Marshall
发明人： Paul R. Marshall
IPC分类号： H03D324
CPC分类号： H03L7/14 , H03L7/0802 , H03L2207/08 , H03L2207/18
摘要： A phase locked loop frequency (PLL) synthesizer in which the scaled output of a reference oscillator(24) is compared with the scaled output of a voltage controlled oscillator(VCO)(10) in a comparator(22) to provide an error voltage which is integrated to form a frequency control voltage for the VCO. When the VCO has stabilized, the PLL is interrupted by the opening of a switch(32) in the output circuit of the comparator(22) and de-energizing the reference oscillator(24), scalers(18,26) and the comparator(22). A capacitor(36) which has been charged by the frequency control voltage maintains the output frequency of the VCO. Periodically the de-energized stages are re-energized and the switch(32) is closed to restore the PLL thereby enabling the VCO(10) to stabilize again after which the cycle of operations is repeated. A technique is disclosed for avoiding a jump in the VCO frequency when the switch(32) is closed.
摘要翻译：锁相环频率（PLL）合成器，其中参考振荡器（24）的缩放输出与比较器（22）中的压控振荡器（VCO）（10）的缩放输出进行比较，以提供误差电压，被集成以形成VCO的频率控制电压。当VCO稳定时，通过在比较器（22）的输出电路中断开开关（32）并使参考振荡器（24），定标器（18,26）和比较器 22）。已经通过频率控制电压充电的电容器（36）保持VCO的输出频率。周期性地，断电阶段被重新通电并且开关（32）闭合以恢复PLL，从而使得VCO（10）能够再次稳定，之后重复操作周期。公开了一种用于在开关（32）关闭时避免VCO频率的跳跃的技术。

5. 发明授权

US07174136B2 Direct conversion radio transceiver 有权
标题翻译：直接转换收音机
公开(公告)号：US07174136B2
公开(公告)日：2007-02-06
申请号：US10082866
申请日：2001-10-19
申请人： Paul R. Marshall , Anthony D. Sayers
发明人： Paul R. Marshall , Anthony D. Sayers
IPC分类号： H04B1/44
CPC分类号： H04B1/403
摘要： A radio transceiver capable of transmitting and receiving on a common radio channel in a half duplex mode includes a direct conversion transmitter and a low IF receiver. A common signal generator (2, 2′, 2″) comprises a first and second frequency generator (40, 41). The first frequency generator generates a carrier frequency signal which is used by both the transmitter and receiver. During reception, the second frequency generator generates an offset signal at the low IF frequency which is mixed with the carrier frequency signal to form a down conversion signal. During transmission, modulation is applied either directly to the carrier frequency signal in one embodiment, or to the offset signal which is then mixed with the carrier frequency signal to form a modulated carrier frequency signal in another embodiment.
摘要翻译：能够以半双工模式在公共无线电信道上发送和接收的无线电收发机包括直接转换发射机和低IF接收机。公共信号发生器（2,2'，2“）包括第一和第二频率发生器（40,41）。第一频率发生器产生由发射机和接收机使用的载频信号。在接收期间，第二频率发生器产生与载波频率信号混合的低IF频率处的偏移信号，以形成降频转换信号。在传输期间，在一个实施例中将调制直接应用于载波频率信号，或者在另一实施例中将偏移信号与载波频率信号混合以形成调制的载波频率信号。

6. 发明授权

US07151767B2 Method and apparatus for synchronizing frequency hopping transceivers 有权
标题翻译：用于同步跳频收发器的方法和装置
公开(公告)号：US07151767B2
公开(公告)日：2006-12-19
申请号：US10024779
申请日：2001-12-20
申请人： Adrian G. Spencer , Paul R. Marshall , Anthony D. Sayers
发明人： Adrian G. Spencer , Paul R. Marshall , Anthony D. Sayers
IPC分类号： H04J1/00
CPC分类号： H04B1/7156 , H04B2001/71563
摘要： A slave radio transceiver for use in a frequency hopping radio system synchronizes by receiving on a sequence of simultaneous combinations of radio channels until a paging message is received from a master transceiver, and may then revert to single channel frequency hopping operation. The slave's multi-channel receiver is sub-equipped to receive simultaneously on a only sub-set (PF12, PF13) of the channels within its bandwidth, the received channels being selected by independent programming within the bandwidth. The channels received simultaneously may be selected to correspond to different degrees of misalignment between the master and slave.
摘要翻译：用于跳频无线电系统的从属无线电收发器通过在无线电信道的同时组合的序列上的接收来同步，直到从主收发器接收到寻呼消息，然后可以恢复为单信道跳频操作。从机的多通道接收机被配备成在其带宽内的通道的唯一子集（PF 12，PF 13）上同时接收，所接收的信道由带宽内的独立编程选择。可以选择同时接收的通道以对应于主机和从机之间不同的不对准程度。

7. 发明授权

US08359051B2 Wireless master-slave distributed communications network 有权
公开(公告)号：US08359051B2
公开(公告)日：2013-01-22
申请号：US10145665
申请日：2002-05-15
申请人： Ian A. Marsden , Paul R. Marshall
发明人： Ian A. Marsden , Paul R. Marshall
IPC分类号： H04B7/00
CPC分类号： H04W84/20 , H04W8/26 , H04W88/04
摘要： A master-slave distributed communications network comprises a master node (10), a plurality of slave nodes (12 to 22), and links (VL) operatively interconnecting the slave nodes and the master node in accordance with a routing plan. Each slave node has means for storing an address of the next node in the routing plan for a message to be routed on an uplink to the master node and when sending a data packet to the master node it appends the prestored address and forwards the data packet to the next node. If the next node is not the master node, it, in turn, adds the prestored address of the next following slave node to the data packet thus lengthening the data packet and re-transmits it, and so on until the data packet reaches the master node.For a downlink message, the master node (10) using a prestored routing table includes in the data packet the addresses of all the slave nodes on the selected route. As the data packet is progressed from slave node to slave node, the address of each slave node which has forwarded the data packet is deleted thus shortening the overall length of the data packet.

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