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1. 发明授权

US07861059B2 Method for testing and programming memory devices and system for same 有权
标题翻译：用于测试和编程存储器件和系统的方法
公开(公告)号：US07861059B2
公开(公告)日：2010-12-28
申请号：US11051325
申请日：2005-02-03
申请人： Paul Magliocco , Young Cheol Kim , Richard Mark Greene , John M. Holmes
发明人： Paul Magliocco , Young Cheol Kim , Richard Mark Greene , John M. Holmes
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C29/56004 , G11C29/56 , G11C29/56008 , G11C29/76 , G11C2029/1806 , G11C2029/2602
摘要： A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successively the first address to the first memory device and the second address to the second memory device. The first address refers to a first group of storage locations in the first memory device and the second address refers to a second group of storage locations in the second memory device. The method then proceeds to load in parallel a string of data to the first and second memory devices so that the string of data is written simultaneously to the first group of storage locations in the first memory device and to the second group of storage locations in the second memory device.
摘要翻译：提供了一种方法和系统，用于对并行布置的多个存储器件进行编程。在本发明的一个实施例中，多个存储器件包括第一和第二存储器件，并且该方法包括连续提供第一地址到第一存储器件，第二地址提供给第二存储器件。第一地址是指第一存储设备中的第一组存储位置，第二地址是指第二存储设备中的第二组存储位置。然后，该方法继续并行地将一串数据加载到第一和第二存储器设备，使得数据串被同时写入第一存储器设备中的第一组存储位置和第二组存储位置第二存储设备。

2. 发明授权

US06754868B2 Semiconductor test system having double data rate pin scrambling 有权
标题翻译：具有双数据速率引脚扰码的半导体测试系统
公开(公告)号：US06754868B2
公开(公告)日：2004-06-22
申请号：US09895439
申请日：2001-06-29
申请人： Steven R. Bristow , Paul Magliocco , Seth W. Craighead
发明人： Steven R. Bristow , Paul Magliocco , Seth W. Craighead
IPC分类号： G01R3128
CPC分类号： G01R31/31917 , G01R31/31919 , G01R31/31921 , G01R31/31922
摘要： A method and apparatus are provided for high speed testing of devices having either logic circuits, memory arrays or both. Apparatus (100) includes: (i) pin electronics (P/Es 145) each coupling the apparatus to one of a number of pins (115) on device (110); (ii) timing and format circuits (T/Fs 150) for mapping a signal to one of P/Es (100); (iii) pattern generator (140) having a number of outputs for outputting signals for testing device (110); (iv) pin scrambling circuit (155) between pattern generator (140) and T/Fs (150), the pin scrambling circuit capable of mapping at least two signals from any of the pattern generator outputs to any of the T/Fs; and (v) clock (135) for providing a clock signal having a clock cycle to pattern generator (140) and T/Fs (150). T/Fs (150) are capable of switching the signals coupled to P/Es (100) at least twice each clock cycle.
摘要翻译：提供了一种方法和装置，用于具有逻辑电路，存储器阵列或两者的装置的高速测试。装置（100）包括：（i）每个将装置连接到装置（110）上的多个销（115）中的一个的销电子装置（P / Es145）; （ii）用于将信号映射到P / Es（100）之一的定时和格式电路（T / Fs 150）; （iii）具有多个用于输出测试装置（110）的信号的输出的模式发生器（140）; （iv）在模式发生器（140）和T / F（150）之间的引脚加扰电路（155），所述引脚加扰电路能够将来自任何模式发生器输出的至少两个信号映射到任何T / F; 和（v）时钟（135），用于向模式发生器（140）和T / F（150）提供具有时钟周期的时钟信号。 T / F（150）能够将每个时钟周期至少两次切换耦合到P / Es（100）的信号。

3. 发明授权

US07003697B2 Apparatus having pattern scrambler for testing a semiconductor device and method for operating same 失效
公开(公告)号：US07003697B2
公开(公告)日：2006-02-21
申请号：US10039738
申请日：2002-01-04
申请人： Paul Magliocco
发明人： Paul Magliocco
IPC分类号： G06F11/00
CPC分类号： G01R31/31924 , G01R31/3183 , G01R31/318307 , G01R31/31919
摘要： A system and method are provided for testing electronic devices. Generally, the system includes: (i) a pattern memory with outputs for storing and outputting bits to the device; and (ii) a pattern scrambler for coupling bits from the outputs to pins on the device to provide a test pattern to the device having a width of from 1 bit to a width equal to the number of outputs. Preferably, the system includes a clock with a clock cycle, and the scrambler can change the width and/or depth of the test pattern on a cycle-by-cycle basis More preferably, the scrambler can change the bits coupled to one or more of the pins on a cycle-by-cycle basis. In one embodiment, the memory simultaneously provides logic vector memory and scan memory for storing logic and scan vectors respectively, and the width/depth of the vectors can be changed on a cycle-by-cycle basis.

4. 发明授权

US07385385B2 System for testing DUT and tester for use therewith 有权
标题翻译：用于测试DUT和测试仪的系统用于此
公开(公告)号：US07385385B2
公开(公告)日：2008-06-10
申请号：US10170916
申请日：2002-06-12
申请人： Paul Magliocco , Ray Wakefield , Paul G. Trudeau
发明人： Paul Magliocco , Ray Wakefield , Paul G. Trudeau
IPC分类号： G01R31/02
CPC分类号： G01R31/31912 , G01R31/31903 , G01R31/31907
摘要： A tester configured to stack with at least one other tester to provide a test system for simultaneously testing a number of devices in parallel on different testers, or testing a device having more pins than can be accommodated by a single tester. The tester includes a test site with a number of pin electronics channels, an interface for interfacing with the device, and a computer for interfacing with a host computer in the test system. The testers can be fastened directly to one another or to a common frame. Preferably, the interface enables a single device board to simultaneously engage interfaces on multiple testers. More preferably, the interface extends from a top surface of the tester to engage the device board. Vents in top and front surfaces of an enclosure enables movement of air to cool components of the tester without interference from testers on either side or a back of the enclosure.
摘要翻译：测试器被配置为与至少一个其他测试器堆叠以提供用于在不同测试器上并行测试多个设备的测试系统，或测试具有比单个测试仪可容纳的引脚多的引脚的器件。测试器包括具有多个引脚电子通道的测试站点，用于与该设备进行接口的接口以及用于与测试系统中的主机连接的计算机。测试人员可以直接相互固定或共同固定。优选地，该接口使得单个设备板能够同时接合多个测试器上的接口。更优选地，界面从测试器的顶表面延伸以接合设备板。外壳的顶面和前表面的通风口可以将空气移动到冷却器的部件，而不会受到外壳两侧或背面的测试仪的干扰。

5. 发明申请

US20050193233A1 Method for testing and programming memory devices and system for same 有权
标题翻译：用于测试和编程存储器件和系统的方法
公开(公告)号：US20050193233A1
公开(公告)日：2005-09-01
申请号：US11051325
申请日：2005-02-03
申请人： Paul Magliocco , Young Kim , Richard Greene , John Holmes
发明人： Paul Magliocco , Young Kim , Richard Greene , John Holmes
IPC分类号： G06F11/00
CPC分类号： G11C29/56004 , G11C29/56 , G11C29/56008 , G11C29/76 , G11C2029/1806 , G11C2029/2602
摘要： A method and system are provided for programming a plurality of memory devices arranged in parallel. In one embodiment of the present invention, the plurality of memory devices comprises first and second memory devices, and the method comprises providing successively the first address to the first memory device and the second address to the second memory device. The first address refers to a first group of storage locations in the first memory device and the second address refers to a second group of storage locations in the second memory device. The method then proceeds to load in parallel a string of data to the first and second memory devices so that the string of data is written simultaneously to the first group of storage locations in the first memory device and to the second group of storage locations in the second memory device.
摘要翻译：提供了一种方法和系统，用于对并行布置的多个存储器件进行编程。在本发明的一个实施例中，多个存储器件包括第一和第二存储器件，并且该方法包括连续提供第一地址到第一存储器件，第二地址提供给第二存储器件。第一地址是指第一存储设备中的第一组存储位置，第二地址是指第二存储设备中的第二组存储位置。然后，该方法继续并行地将一串数据加载到第一和第二存储器设备，使得数据串被同时写入第一存储器设备中的第一组存储位置和第二组存储位置第二存储设备。

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