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1. 发明授权

US08565135B2 Power management of wireless protocol circuitry based on current state 失效
标题翻译：基于当前状态的无线协议电路的电源管理
公开(公告)号：US08565135B2
公开(公告)日：2013-10-22
申请号：US12970739
申请日：2010-12-16
申请人： Paul J. Husted , Brian J. Kaczynski , Soner Ozgur
发明人： Paul J. Husted , Brian J. Kaczynski , Soner Ozgur
IPC分类号： G08C17/00 , H04W4/00
CPC分类号： H04W52/0229 , Y02D70/142 , Y02D70/144 , Y02D70/162 , Y02D70/166
摘要： Controlling power consumption in a wireless device. The wireless device may include first wireless protocol circuitry. The first wireless protocol circuitry may be configured to receive and process first signals according to a first wireless protocol. The wireless device may include a power controller coupled to the first wireless protocol circuitry. The power controller may be configured to control power consumption of elements of the first wireless protocol circuitry based on a current state. More specifically, in response to the first wireless protocol circuitry being in a listening state, the power controller may be configured to lower power consumption of one or more first elements of the first wireless protocol circuitry. Additionally, in response to the first wireless protocol circuitry being in a receiving state, the power controller may be configured to return power consumption of the one or more first elements to a higher power level.
摘要翻译：控制无线设备的功耗。无线设备可以包括第一无线协议电路。第一无线协议电路可以被配置为根据第一无线协议接收和处理第一信号。无线设备可以包括耦合到第一无线协议电路的功率控制器。功率控制器可以被配置为基于当前状态来控制第一无线协议电路的元件的功率消耗。更具体地，响应于第一无线协议电路处于监听状态，功率控制器可以被配置为降低第一无线协议电路的一个或多个第一元件的功耗。另外，响应于第一无线协议电路处于接收状态，功率控制器可以被配置为将一个或多个第一元件的功率消耗返回到更高的功率水平。

2. 发明申请

US20120155347A1 POWER MANAGEMENT OF WIRELESS PROTOCOL CIRCUITRY BASED ON CURRENT STATE 失效
标题翻译：基于当前状态的无线协议电路的电源管理
公开(公告)号：US20120155347A1
公开(公告)日：2012-06-21
申请号：US12970739
申请日：2010-12-16
申请人： Paul J. Husted , Brian J. Kaczynski , Soner Ozgur
发明人： Paul J. Husted , Brian J. Kaczynski , Soner Ozgur
IPC分类号： H04W52/02
CPC分类号： H04W52/0229 , Y02D70/142 , Y02D70/144 , Y02D70/162 , Y02D70/166
摘要： Controlling power consumption in a wireless device. The wireless device may include first wireless protocol circuitry. The first wireless protocol circuitry may be configured to receive and process first signals according to a first wireless protocol. The wireless device may include a power controller coupled to the first wireless protocol circuitry. The power controller may be configured to control power consumption of elements of the first wireless protocol circuitry based on a current state. More specifically, in response to the first wireless protocol circuitry being in a listening state, the power controller may be configured to lower power consumption of one or more first elements of the first wireless protocol circuitry. Additionally, in response to the first wireless protocol circuitry being in a receiving state, the power controller may be configured to return power consumption of the one or more first elements to a higher power level.
摘要翻译：控制无线设备的功耗。无线设备可以包括第一无线协议电路。第一无线协议电路可以被配置为根据第一无线协议接收和处理第一信号。无线设备可以包括耦合到第一无线协议电路的功率控制器。功率控制器可以被配置为基于当前状态来控制第一无线协议电路的元件的功率消耗。更具体地，响应于第一无线协议电路处于监听状态，功率控制器可以被配置为降低第一无线协议电路的一个或多个第一元件的功耗。另外，响应于第一无线协议电路处于接收状态，功率控制器可以被配置为将一个或多个第一元件的功率消耗返回到更高的功率水平。

3. 发明授权

US07813711B1 Stacking baseband circuits using deep n-well and increased supply voltage 有权
标题翻译：使用深n阱堆叠基带电路并增加电源电压
公开(公告)号：US07813711B1
公开(公告)日：2010-10-12
申请号：US11688810
申请日：2007-03-20
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： H04B1/28
CPC分类号： H04B1/30 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0084
摘要： A method of designing stacked circuits for an integrated circuit is described. In this method, a plurality of devices that are stackable may be determined. Some of those devices, i.e. a subset of stackable devices, may be formed in a deep n-well, thereby allowing that subset of stackable devices to receive an increased supply voltage. The remainder of the stackable devices may be formed in a standard n-well, thereby allowing such devices to receive a standard supply voltage. In one embodiment, the standard supply voltage may be VDD and the increased supply voltage may be 2×VDD. This method may be advantageously used in both the design of stacked circuits for and the implementation of stacked circuits in an integrated circuit.
摘要翻译：描述了一种设计用于集成电路的堆叠电路的方法。在该方法中，可以确定可堆叠的多个装置。这些设备中的一些，即可堆叠设备的子集，可以形成在深n阱中，从而允许可堆叠设备的子集接收增加的电源电压。可堆叠装置的其余部分可以形成在标准n阱中，从而允许这种装置接收标准电源电压。在一个实施例中，标准电源电压可以是VDD，并且增加的电源电压可以是2×VDD。该方法可有利地用于集成电路中堆叠电路的设计和层叠电路的实现。

4. 发明申请

US20080234848A1 Frequency-tracked synthesizer employing selective harmonic amplification 审中-公开
标题翻译：采用选择性谐波放大的频率跟踪合成器
公开(公告)号：US20080234848A1
公开(公告)日：2008-09-25
申请号：US11728121
申请日：2007-03-23
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： G06F17/00
CPC分类号： G10H1/08 , G10H7/105 , G10H2250/235 , G10H2250/471 , H04S1/007
摘要： This invention relates to effects processing of a monophonic analog signal, meaning a signal whose frequency components are all integer multiples of a first fundamental frequency. For example, the signal could come from almost any musical instrument, voice included. However, for generality, the invention is not restricted to cases where the signal source is musical. The digital signal processing is simplified as a result of the DSP being clocked at a constant multiple of ffund. This means that the sine and cosine functions, as well as the low-pass filters which make up each harmonic selector, are trivial to implement because the frequencies of each sine/cosine, as well as the cutoff frequency of the low-pass filters, are constant fractions of the DSP clock frequency.
摘要翻译：本发明涉及单声道模拟信号的效果处理，意思是其频率分量均为第一基频的整数倍的信号。例如，信号可能来自几乎任何乐器，包括声音。然而，为了一般性，本发明不限于信号源是音乐的情况。数字信号处理被简化为DSP以恒定倍数的频率计时的结果。这意味着构成每个谐波选择器的正弦和余弦函数以及低通滤波器由于每个正弦/余弦的频率以及低通滤波器的截止频率都是微不足道的，是DSP时钟频率的不变部分。

5. 发明授权

US07400691B2 Power control on a packet-by-packet basis in a CMOS transceiver 有权
标题翻译：在CMOS收发器中逐个分组地进行功率控制
公开(公告)号：US07400691B2
公开(公告)日：2008-07-15
申请号：US11621081
申请日：2007-01-08
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： H04K1/02
CPC分类号： H04W52/362 , H03F1/223 , H03F3/24 , H03F3/45475 , H03F2203/45128 , H03F2203/45274 , H03G3/3042 , H04B2001/0416 , H04W52/286 , H04W52/367 , H04W52/52
摘要： A transceiver includes a power control circuit in the transmitter that operates on a packet-by-packet basis. The transceiver can, for each packet, set a variable gain amplifier to a first gain and use predetermined gain increments to thereafter increase gain until a gain hold event. The gain hold event can be an expiration of a time duration allocated for changing gain or a desired power being reached, whichever event occurs first. The gain can be adjusted by a predetermined amount based on an operating condition.
摘要翻译：收发器包括发射机中的功率控制电路，其基于逐个分组地操作。对于每个分组，收发器可以将可变增益放大器设置为第一增益，并且使用预定的增益增量，此后增加增益直到增益保持事件。增益保持事件可以是分配用于改变增益或期望的功率的时间段的到期，无论哪个事件首先发生。可以基于操作条件将增益调整预定量。

6. 发明授权

US07982518B1 Controlling timing in asynchronous digital circuits 有权
标题翻译：异步数字电路控制时序
公开(公告)号：US07982518B1
公开(公告)日：2011-07-19
申请号：US12026535
申请日：2008-02-05
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1515 , H03M1/462
摘要： A timing circuit for generating asynchronous signals is provided that uses minimal area while maximizing speed. This timing circuit can include a timing control block and disable/enable circuitry. The timing control block can include an SR latch and first and second delay blocks. The SR latch can generate first and second signals, wherein the first and second signals are asynchronous. The first delay block can generate a delayed first signal and provide that signal to a first input terminal of the SR latch. Similarly, the second delay block can generate a delayed second signal and provide that signal to a second input terminal of the SR latch. Notably, the first and second delay blocks delay positive going edges of the first and second signals differently than negative going edges of the first and second signals.
摘要翻译：提供用于产生异步信号的定时电路，其使最小面积同时最大化速度。该定时电路可以包括定时控制块和禁用/使能电路。定时控制块可以包括SR锁存器和第一和第二延迟块。 SR锁存器可以产生第一和第二信号，其中第一和第二信号是异步的。第一延迟块可以产生延迟的第一信号并将该信号提供给SR锁存器的第一输入端。类似地，第二延迟块可以产生延迟的第二信号并将该信号提供给SR锁存器的第二输入端。值得注意的是，第一和第二延迟块延迟第一和第二信号的正向边沿不同于第一和第二信号的负沿边缘。

7. 发明授权

US07768363B1 Inter-stage coupling with a transformer and parallel AC-coupling capacitor 有权
标题翻译：与变压器和并联交流耦合电容器的级间耦合
公开(公告)号：US07768363B1
公开(公告)日：2010-08-03
申请号：US11847268
申请日：2007-08-29
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： H01P5/04 , H03H7/01
CPC分类号： H03H7/38 , H03F3/189 , H03F2200/411 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541
摘要： An RF coupling circuit including a transformer and a parallel AC-coupling capacitor can advantageously ameliorate substantial attenuation of a signal, prevent destabilization of any feedback loop, and simplify the circuit design process. The AC-coupling capacitor can act as an “averager”, i.e. both the input and output sides of coupling circuit represent capacitances equal to the average of the input and the output capacitances. Thus, the inductors for tuning them out can become equal, thereby allowing a symmetric (or near symmetric) transformer to be used in the RF coupling circuit. When tuned properly, the transformer plus AC-coupling capacitor can also advantageously provide better in-band gain as well as frequency selectivity than other conventional coupling circuits.
摘要翻译：包括变压器和并联AC耦合电容器的RF耦合电路可以有利地改善信号的实质衰减，防止任何反馈回路的不稳定，并简化电路设计过程。 AC耦合电容器可以作为“平均器”，即耦合电路的输入和输出侧都表示与输入和输出电容的平均值相等的电容。因此，用于调谐它们的电感器可以变得相等，从而允许在RF耦合电路中使用对称（或近似对称的）变压器。当正确调谐时，变压器加交流耦合电容器还可以有利地提供比其他常规耦合电路更好的带内增益以及频率选择性。

8. 发明授权

US07065155B2 Method and apparatus for a transceiver having a constant power output 有权
公开(公告)号：US07065155B2
公开(公告)日：2006-06-20
申请号：US09927425
申请日：2001-08-10
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： H04K1/02 , H04L25/03 , H04L25/49
CPC分类号： H04W52/362 , H03F1/223 , H03F3/24 , H03F3/45475 , H03F2203/45128 , H03F2203/45274 , H03G3/3042 , H04B2001/0416 , H04W52/286 , H04W52/367 , H04W52/52
摘要： The present invention includes a transceiver and a method of operating the same that includes in the transmitter a power control circuit that operates on an analog differential signal containing data packets individually. The power control circuit initially transmits a series of data symbols with known values, periodically strobes the transceiver system for correct power levels and incrementally increases the power level of the transceiver until the optimal gain is reached, without exceeding the maximum output power.

9. 发明申请

US20110299704A1 Frequency-tracked synthesizer employing selective harmonic amplification and/or frequency scaling 审中-公开
标题翻译：采用选择性谐波放大和/或频率缩放的频率跟踪合成器
公开(公告)号：US20110299704A1
公开(公告)日：2011-12-08
申请号：US13136935
申请日：2011-08-15
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： H03G5/00 , H03F99/00
CPC分类号： G10H1/08 , G10H7/105 , G10H2250/235 , G10H2250/471 , H04S1/007
摘要： This invention relates to effects processing of a monophonic analog signal, meaning a signal whose frequency components are all integer multiples of a first fundamental frequency. For example, the signal could come from almost any musical instrument, voice included. However, for generality, the invention is not restricted to cases where the signal source is musical. The digital signal processing is simplified as a result of the DSP being clocked at a constant multiple of ffund. This means that the sine and cosine functions, as well as the low-pass filters which make up each harmonic selector, are trivial to implement because the frequencies of each sine/cosine, as well as the cutoff frequency of the low-pass filters, are constant fractions of the DSP clock frequency.
摘要翻译：本发明涉及单声道模拟信号的效果处理，意思是其频率分量均为第一基频的整数倍的信号。例如，信号可能来自几乎任何乐器，包括声音。然而，为了一般性，本发明不限于信号源是音乐的情况。数字信号处理由于DSP以恒定的ffund倍频计时，因此被简化。这意味着构成每个谐波选择器的正弦和余弦函数以及低通滤波器由于每个正弦/余弦的频率以及低通滤波器的截止频率都是微不足道的，是DSP时钟频率的不变部分。

10. 发明申请

US20080232526A1 Digital signal processing employing a clock frequency which is always a constant integer multiple of the fundamental frequency of an input analog signal 审中-公开
标题翻译：使用始终为输入模拟信号的基频的常数整数倍的时钟频率的数字信号处理
公开(公告)号：US20080232526A1
公开(公告)日：2008-09-25
申请号：US11728147
申请日：2007-03-23
申请人： Brian J. Kaczynski
发明人： Brian J. Kaczynski
IPC分类号： H04L7/04
CPC分类号： H03L7/18 , H03H7/12 , H03H11/1291 , H03L7/00 , H03L7/14
摘要： A method and apparatus are disclosed for clocking a DSP at a frequency which is always a constant integer multiple of the fundamental frequency of the input analog signal. This invention applies in situations where the analog signal exhibits certain characteristics in which a fixed clock frequency is not desired, but rather what is needed is a clock which tracks the fundamental frequency of the analog signal, for example, a signal from a monophonic musical instrument or a polyphonic instrument being played one note at a time.
摘要翻译：公开了一种用于以始终为输入模拟信号的基频的恒定整数倍的频率对DSP计时的方法和装置。本发明适用于模拟信号表现出不期望固定时钟频率的某些特性的情况，而需要的是跟踪模拟信号的基频的时钟，例如来自单声乐器的信号或同时播放一个音符的复音乐器。

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