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1. 发明授权

US5304958A Saw oscillator gain amplifier with auto phase shift 失效
标题翻译：带自动相移的振荡器增益放大器
公开(公告)号：US5304958A
公开(公告)日：1994-04-19
申请号：US979677
申请日：1992-11-20
申请人： Paul B. Sofianos , Phuc C. Pham , Dwight D. Esgar
发明人： Paul B. Sofianos , Phuc C. Pham , Dwight D. Esgar
IPC分类号： H03B5/30 , H03B5/32 , H03K3/014 , H03K3/03 , H03L7/06 , H03B5/12
CPC分类号： H03K3/014 , H03B5/326 , H03K3/0307 , Y10S331/03
摘要： A gain stage for providing an automatic phase shift is provided. In particular, the gain stage detects whether an oscillation signal appears at its inputs. If an oscillation signal is not detected, then the gain stage inverts output signals occurring at outputs of a first amplifier before being respectively applied to inputs of a second amplifier. This has the overall effect of implementing a 180.degree. phase shift of a signal appearing at the outputs of the gain stage with respect to a signal appearing at the inputs of the gain stage.
摘要翻译：提供了一种用于提供自动相移的增益级。特别地，增益级检测振荡信号是否出现在其输入端。如果没有检测到振荡信号，则增益级在分别施加到第二放大器的输入之前将在第一放大器的输出处发生的输出信号反相。这具有相对于在增益级的输入处出现的信号实现在增益级的输出处出现的信号的180度相移的总体效果。

2. 发明授权

US5444395A Non-saturating bipolar transistor circuit 失效
标题翻译：非饱和双极晶体管电路
公开(公告)号：US5444395A
公开(公告)日：1995-08-22
申请号：US161559
申请日：1993-12-06
申请人： Dwight D. Esgar , Ray D. Sundstrom , Phuc C. Pham
发明人： Dwight D. Esgar , Ray D. Sundstrom , Phuc C. Pham
IPC分类号： H03K17/0422 , H03K19/013 , H03K19/018 , H03K19/0175 , H03K17/04
CPC分类号： H03K19/01812 , H03K17/0422 , H03K19/013
摘要： A non-saturating transistor circuit (11) having a first terminal (13), a control terminal (12), and a second terminal (14). The first terminal (13), control terminal (12), and second terminal (14) correspond respectively to a collector, base, and emitter of a transistor. The non-saturating transistor circuit (11) comprises a voltage divider (15), a diode (19), and a transistor (16). The voltage divider (15) enables the transistor (16) when a voltage is applied across the control terminal (12) and the second terminal (14) of non-saturating transistor circuit (11). The diode (19) removes current drive to the transistor (16) prior to the transistor (16) becoming saturated thus preventing the transistor (16) from saturating under all operating conditions.
摘要翻译：具有第一端子（13），控制端子（12）和第二端子（14）的非饱和晶体管电路（11）。第一端子（13），控制端子（12）和第二端子（14）分别对应于晶体管的集电极，基极和发射极。非饱和晶体管电路（11）包括分压器（15），二极管（19）和晶体管（16）。当跨越控制端子（12）和非饱和晶体管电路（11）的第二端子（14）施加电压时，分压器（15）使得晶体管（16）能够被施加。在晶体管（16）饱和之前，二极管（19）去除对晶体管（16）的电流驱动，从而防止晶体管（16）在所有工作条件下饱和。

3. 发明授权

US5627492A Circuit and method for isolating circuit blocks for reducing power dissipation 失效
标题翻译：用于隔离电路块以降低功耗的电路和方法
公开(公告)号：US5627492A
公开(公告)日：1997-05-06
申请号：US552709
申请日：1995-11-03
申请人： Mark Weaver , Robert D. Berger , Dwight D. Esgar
发明人： Mark Weaver , Robert D. Berger , Dwight D. Esgar
IPC分类号： H03K19/00 , G05F1/10
CPC分类号： H03K19/0008
摘要： An integrated circuit is divided into functional blocks. The integrated circuit includes current source based circuitry such as Emitter Coupled Logic (ECL), Current Mode Logic (CML), or Source Coupled Logic (SCL) Isolation blocks (14-20) are placed in signal paths to and from each functional block. A multiple output bias driver circuit (13) couples to each functional block. The multiple output bias driver circuit (13) provides a signal for enabling and disabling current sources of a functional block. A bias control logic circuit (12) controls the isolation blocks (14-20) and the multiple output bias driver (13). A functional block that is idle in the operation of the integrated circuit is shut down by the bias control logic circuit (12) to conserve power. The multiple output bias driver circuit (13) receives control signals from the bias control logic circuit (12) to turn off current sources in the idle functional block. Isolation blocks (14-20) receive control signals from the bias control logic circuit (12) to isolate the idle functional block and to provide a predetermined logic level in the signal paths from the idle functional to prevent propagation of an erroneous signal.
摘要翻译：集成电路分为功能块。集成电路包括基于电流源的电路，例如发射极耦合逻辑（ECL），电流模式逻辑（CML）或源耦合逻辑（SCL）隔离块（14-20）放置在到每个功能块的信号路径中。多输出偏置驱动器电路（13）耦合到每个功能块。多输出偏置驱动器电路（13）提供用于启用和禁用功能块的电流源的信号。偏置控制逻辑电路（12）控制隔离块（14-20）和多输出偏置驱动器（13）。在集成电路的操作中空闲的功能块被偏置控制逻辑电路（12）关断以节省功率。多输出偏置驱动器电路（13）从偏置控制逻辑电路（12）接收控制信号以关闭空闲功能块中的电流源。隔离块（14-20）接收来自偏置控制逻辑电路（12）的控制信号以隔离空闲功能块并且提供来自空闲功能的信号路径中的预定逻辑电平以防止错误信号的传播。

4. 发明授权

US4994690A Split level bus 失效
标题翻译：分层公交车
公开(公告)号：US4994690A
公开(公告)日：1991-02-19
申请号：US471581
申请日：1990-01-29
申请人： Ray D. Sundstrom , Cleon Petty , Dwight D. Esgar
发明人： Ray D. Sundstrom , Cleon Petty , Dwight D. Esgar
IPC分类号： G06F13/36 , G06F13/40 , H04L12/40 , H04L25/02
CPC分类号： H04L25/0272 , G06F13/4072 , H04L12/40 , H04L25/0298
摘要： A split level differential bus having first and second signals at first and second lines, respectively, for transmitting data from a typical driver to a typical receiver, includes a first independent voltage source for terminating the first line and a second independent voltage source for terminating the second line, the second independent voltage source providing a voltage level that is different from the voltage level provided by the first independent voltage source. A current switch circuit controlled by the driver for switching current from the first line to the second line. A level shifting circuit coupled between the first line and the receiver for level shifting the first signal by a predetermined voltage.

5. 发明授权

US4980581A Differential ECL bus tri-state detection receiver 失效
标题翻译：差分ECL总线三态检测接收器
公开(公告)号：US4980581A
公开(公告)日：1990-12-25
申请号：US526267
申请日：1990-05-21
申请人： Dwight D. Esgar , Ray D. Sundstrom
发明人： Dwight D. Esgar , Ray D. Sundstrom
IPC分类号： H03K19/0175 , H03K3/2893 , H03K5/24 , H03K19/086
CPC分类号： H03K3/2893 , H03K5/2418
摘要： A circuit having first and second inputs and first and second outputs includes a differential receiver circuit responsive to the first and second inputs for providing corresponding output logic signals at the first and second outputs. A tri-state detection circuit responsive to the first and second inputs and having an output for providing a first predetermined voltage to the differential receiver circuit when the first and second inputs are in a normal mode and for providing an increased second predetermined voltage to the differential receiver circuit when the first and second inputs are in a tri-state mode wherein oscillation of the differential receiver circuit is prevented and the outputs are forced to known logic states while the noise margin of the differential receiver is increased without a sacrifice in common mode range.
摘要翻译：具有第一和第二输入以及第一和第二输出的电路包括响应于第一和第二输入的差分接收器电路，用于在第一和第二输出处提供对应的输出逻辑信号。一种三态检测电路，其响应于第一和第二输入，并且具有用于当第一和第二输入处于正常模式时向差分接收器电路提供第一预定电压的输出，并且用于向差分提供增加的第二预定电压当第一和第二输入处于三态模式时，其中防止差分接收器电路的振荡，并且将输出强制为已知的逻辑状态，同时增加差分接收器的噪声容限而不牺牲共模范围。

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