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1. 发明授权

US5950303A Method and fixturing to perform two side laminations of stacked substrates forming 3-D modules 失效
标题翻译：方法和固定以执行形成3-D模块的堆叠衬底的两侧叠层
公开(公告)号：US5950303A
公开(公告)日：1999-09-14
申请号：US056043
申请日：1998-04-03
申请人： Paul A. McConnelee , Richard J. Saia , Kevin M. Durocher
发明人： Paul A. McConnelee , Richard J. Saia , Kevin M. Durocher
IPC分类号： B29C63/00 , H05K1/03 , H05K1/14 , H05K3/40 , H05K3/46 , H05K3/36
CPC分类号： B29C63/0026 , H05K3/403 , B29L2009/00 , H05K1/0306 , H05K1/144 , H05K2201/09581 , H05K2203/0165 , H05K2203/068 , H05K3/4611 , H05K3/4629 , H05K3/4685 , Y10T29/49126 , Y10T29/5317
摘要： A substrate stack is suspended within a stack holder to position upper and lower stack surfaces coplanar with upper and lower holder surfaces. Laminating heat and pressure is simultaneously applied to the upper and lower surfaces to laminate a carrier interconnect film to top and bottom stack portions simultaneously. Subsequent wet chemical processing of both stack edges may also be simultaneous to effect savings in manufacturing costs.
摘要翻译：衬底堆叠悬挂在堆叠保持器内以将上和下堆叠表面定位成与上保持器表面和下保持器表面共面。叠层热和压力同时施加到上表面和下表面，以将载体互连膜同时层叠到顶部和底部堆叠部分。随后的两个堆叠边缘的湿化学处理也可以同时实现制造成本的节省。

2. 发明授权

US5524339A Method for protecting gallium arsenide mmic air bridge structures 失效
标题翻译：砷化镓空气桥梁结构的保护方法
公开(公告)号：US5524339A
公开(公告)日：1996-06-11
申请号：US308886
申请日：1994-09-19
申请人： Bernard Gorowitz , Richard J. Saia , Kevin M. Durocher
发明人： Bernard Gorowitz , Richard J. Saia , Kevin M. Durocher
IPC分类号： H01L23/00 , H01L23/29 , H01L23/31 , H01L23/538 , H01L23/66 , H05K3/30
CPC分类号： H01L23/562 , H01L23/29 , H01L23/315 , H01L23/5385 , H01L23/5389 , H01L23/66 , H01L24/24 , H01L24/82 , H01L2224/24227 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/1423 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/3011 , H01L2924/3025 , Y10T29/49144 , Y10T29/49146
摘要： In a method for preserving an air bridge structure on an integrated circuit chip, a protective layer is plasma-deposited over the top and sides of the air bridge. A high density interconnect structure is applied over the chip and protective layer. The protective film provides mechanical strength during the application of the high density interconnect structure to prevent deformation. It also prevents any contamination from intruding under the air bridge. More importantly, the protective film only negligibly impedes the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure.
摘要翻译：在一种用于在集成电路芯片上保持空气桥结构的方法中，保护层被等离子体沉积在空气桥的顶部和侧面上。在芯片和保护层上施加高密度互连结构。保护膜在应用高密度互连结构期间提供机械强度以防止变形。它还可以防止任何污染物侵入空气桥下。更重要的是，保护膜只能忽略不计地阻碍空气桥的性能，因此不需要去除，从而消除了消除HDI结构的必要性。

3. 发明申请

US20100132994A1 APPARATUS AND METHOD FOR REDUCING PITCH IN AN INTEGRATED CIRCUIT 有权
标题翻译：用于减少集成电路中的电位的装置和方法
公开(公告)号：US20100132994A1
公开(公告)日：2010-06-03
申请号：US12326214
申请日：2008-12-02
申请人： Raymond Albert Fillion , Kevin M. Durocher , Richard Joseph Saia , Paul A. McConnelee
发明人： Raymond Albert Fillion , Kevin M. Durocher , Richard Joseph Saia , Paul A. McConnelee
IPC分类号： H05K1/18 , H05K3/10
CPC分类号： H01L24/82 , H01L21/76804 , H01L21/76816 , H01L23/3114 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/92144 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/19042 , Y10T29/49155
摘要： An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.
摘要翻译：一种装置和方法，该装置包括电子芯片封装，其包括电子芯片，该电子芯片具有第一接触焊盘和第二接触焊盘，并且在其之间没有中间接触焊盘，第一介电层在第一和第二接触焊盘上耦合到电子芯片，第二接触焊盘和耦合到第一介电层的第二介电层，使得在它们之间形成介电层边界。第一电介质层具有在对应于第一接触焊盘并向下延伸的第一位置处穿过其形成的第一接触焊盘通孔。第二电介质层具有在对应于第二接触焊盘并向下延伸的第二位置处穿过其形成的第二接触焊盘通孔，使得在第二位置处形成第二接触焊盘多层通孔，所述第二接触焊盘多层通孔穿过第一和第二电介质层，到第二接触垫。

4. 发明授权

US06709944B1 Techniques for fabricating a resistor on a flexible base material 有权
标题翻译：在柔性基材上制造电阻器的技术
公开(公告)号：US06709944B1
公开(公告)日：2004-03-23
申请号：US10261052
申请日：2002-09-30
申请人： Kevin M. Durocher , Richard J. Saia , Vikram B. Krishnamurthy
发明人： Kevin M. Durocher , Richard J. Saia , Vikram B. Krishnamurthy
IPC分类号： H01L2702
CPC分类号： H01C17/12 , B29C59/14 , H01C7/006 , H05K1/0346 , H05K1/167 , H05K3/381 , H05K3/388 , H05K2201/0154 , H05K2201/0317 , H05K2203/095 , H05K2203/1136
摘要： A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
摘要翻译：一种在柔性基板上制造电阻器的技术。具体地，通过暴露于离子溅射蚀刻技术来活化聚酰亚胺基底的至少一部分。金属层设置在基板的激活部分上，从而形成高电阻金属碳化物区域。互连层设置在金属碳化物区域上并被图案化以在金属碳化物区域的相对端形成端子。将金属碳化物区域图案化以在端子之间形成电阻器。或者，仅激活聚酰亚胺基板的选定区域。所选区域形成形成金属碳化物区域的区域。互连层设置在金属碳化物区域上并被图案化以在金属碳化物区域的相对端形成端子。

5. 发明授权

US5531018A Method of micromachining electromagnetically actuated current switches with polyimide reinforcement seals, and switches produced thereby 失效
标题翻译：具有聚酰亚胺加强密封的微电机驱动电流开关的微加工方法以及由此产生的开关
公开(公告)号：US5531018A
公开(公告)日：1996-07-02
申请号：US169272
申请日：1993-12-20
申请人： Richard J. Saia , Mario Ghezzo , Bharat S. K. Bagepalli , Kevin M. Durocher
发明人： Richard J. Saia , Mario Ghezzo , Bharat S. K. Bagepalli , Kevin M. Durocher
IPC分类号： B81B3/00 , H01H50/00 , H01H11/00
CPC分类号： B81B7/0012 , H01H50/005 , B81B2201/018 , Y10T29/49105
摘要： An insulating layer with at least one via is provided over a metal plate. A sacrificial layer is applied over a portion of the insulating layer so that the sacrificial layer extends into the via. A metal bridge having at least one opening is provided over a portion of the sacrificial layer and a portion of the insulating layer so that the metal bridge extends over the via and the opening is situated adjacent a portion of the sacrificial layer. A reinforcing seal layer with a well is provided over the metal bridge so that the well is situated adjacent to at least a portion of the opening. The sacrificial layer is then removed.
摘要翻译：具有至少一个通孔的绝缘层设置在金属板上。牺牲层施加在绝缘层的一部分上，使得牺牲层延伸到通孔中。在牺牲层的一部分和绝缘层的一部分上设置具有至少一个开口的金属桥，使得金属桥在通孔上方延伸，并且开口位于牺牲层的一部分附近。在金属桥上提供了具有井的增强密封层，使得井位于与开口的至少一部分相邻的位置。然后去除牺牲层。

6. 发明授权

US5472539A Methods for forming and positioning moldable permanent magnets on electromagnetically actuated microfabricated components 失效
标题翻译：在电磁致动的微制造部件上形成和定位成型永久磁铁的方法
公开(公告)号：US5472539A
公开(公告)日：1995-12-05
申请号：US254725
申请日：1994-06-06
申请人： Richard J. Saia , Kevin M. Durocher , Thomas B. Gorczyca , Mario Ghezzo
发明人： Richard J. Saia , Kevin M. Durocher , Thomas B. Gorczyca , Mario Ghezzo
IPC分类号： H01H50/00 , B32B31/28
CPC分类号： H01H50/005 , H02K99/00 , H01H2050/007
摘要： A low temperature batch method for forming and positioning permanent magnets on electromagnetically actuated micro-fabricated components, such as electrical switches employs a first adhesive, such as a Siltem/epoxy blend of an epoxy resin and a siloxane polyimide polymer, to releasably attach a mold layer of Kapton polyimide to a substrate, which may be the movable portion of a micromechanical structure, or a precursor to such movable portion. A well-shape cavity is formed in the mold layer, and filled with a slurry of rare earth NdFeB magnetic particles suspended in a second adhesive, which is cured to form the body of a magnet. The second adhesive is an SPI/epoxy blend, also of an epoxy resin and a siloxane polyimide polymer, but with a greater adhesion strength and a higher temperature softening point compared to the Siltem/epoxy blend. The entire structure is heated, and the mold layer is pulled off the substrate, while the body of magnetic material remains firmly attached. Selective etchants may be subsequently employed to remove metal sacrificial layers, while the NdFeB magnetic particles are protected from attack by the etchant by being effectively encased in plastic.
摘要翻译：用于在诸如电气开关的电磁致动微制造部件上形成和定位永磁体的低温分批方法采用第一粘合剂，例如环氧树脂的Siltem /环氧共混物和硅氧烷聚酰亚胺聚合物，以可释放地附接模具 Kapton聚酰亚胺层可以是基底，其可以是微机械结构的可移动部分，或者是可移动部分的前体。在模具层中形成良好的形状的空腔，并填充悬浮在第二粘合剂中的稀土NdFeB磁性颗粒的浆料，其被固化以形成磁体的主体。第二种粘合剂是SPI /环氧共混物，也是环氧树脂和硅氧烷聚酰亚胺聚合物，但是与Siltem /环氧树脂共混物相比具有更大的粘合强度和更高的温度软化点。整个结构被加热，并且模具层被拉离基板，而磁性材料的主体保持牢固地附着。随后可以选择性蚀刻剂去除金属牺牲层，同时通过被有效地包裹在塑料中来保护NdFeB磁性颗粒免受蚀刻剂的侵蚀。

7. 发明授权

US07158383B2 Techniques for fabricating a resistor on a flexible base material 有权
标题翻译：在柔性基材上制造电阻器的技术
公开(公告)号：US07158383B2
公开(公告)日：2007-01-02
申请号：US10716143
申请日：2003-11-18
申请人： Kevin M. Durocher , Richard J. Saia , Vikram B. Krishnamurthy
发明人： Kevin M. Durocher , Richard J. Saia , Vikram B. Krishnamurthy
IPC分类号： H05K1/16
CPC分类号： H01C17/12 , B29C59/14 , H01C7/006 , H05K1/0346 , H05K1/167 , H05K3/381 , H05K3/388 , H05K2201/0154 , H05K2201/0317 , H05K2203/095 , H05K2203/1136
摘要： A technique for fabricating a resistor on a flexible substrate. Specifically, at least a portion of a polyimide substrate is activated by exposure to a ion sputter etch techniques. A metal layer is disposed over the activated portion of the substrate, thereby resulting in the formation of a highly resistive metal-carbide region. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal carbide region. The metal-carbide region is patterned to form a resistor between the terminals. Alternatively, only a selected area of the polyimide substrate is activated. The selected area forms the area in which the metal-carbide region is formed. Interconnect layers are disposed over the metal-carbide region and patterned to form terminals at opposite ends of the metal-carbide region.
摘要翻译：一种在柔性基板上制造电阻器的技术。具体地，通过暴露于离子溅射蚀刻技术来活化聚酰亚胺基底的至少一部分。金属层设置在基板的激活部分上，从而形成高电阻金属碳化物区域。互连层设置在金属碳化物区域上并被图案化以在金属碳化物区域的相对端形成端子。将金属碳化物区域图案化以在端子之间形成电阻器。或者，仅激活聚酰亚胺基板的选定区域。所选择的区域形成形成金属碳化物区域的区域。互连层设置在金属碳化物区域上并被图案化以在金属碳化物区域的相对端形成端子。

8. 发明申请

US20100224992A1 SYSTEM AND METHOD FOR STACKED DIE EMBEDDED CHIP BUILD-UP 有权
标题翻译：堆叠式嵌入式嵌入式嵌入式系统和方法
公开(公告)号：US20100224992A1
公开(公告)日：2010-09-09
申请号：US12399083
申请日：2009-03-06
申请人： Paul Alan McConnelee , Kevin M. Durocher , Donald Paul Cunningham
发明人： Paul Alan McConnelee , Kevin M. Durocher , Donald Paul Cunningham
IPC分类号： H01L23/52 , H01L21/50
CPC分类号： H05K1/185 , H01L21/4857 , H01L21/486 , H01L23/3672 , H01L23/5383 , H01L23/5389 , H01L23/642 , H01L23/645 , H01L23/647 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/2402 , H01L2224/24195 , H01L2224/24226 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/83192 , H01L2224/92144 , H01L2224/97 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/1627 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3511 , H05K1/186 , H05K3/386 , H05K3/4644 , H05K2201/0195 , H05K2201/10515 , H05K2201/10674 , H01L2224/82 , H01L2924/00
摘要： An embedded chip package (ECP) includes a plurality of re-distribution layers joined together in a vertical direction to form a lamination stack, each re-distribution layer having vias formed therein. The embedded chip package also includes a first chip embedded in the lamination stack and a second chip attached to the lamination stack and stacked in the vertical direction with respect to the first chip, each of the chips having a plurality of chip pads. The embedded chip package further includes an input/output (I/O) system positioned on an outer-most re-distribution layer of the lamination stack and a plurality of metal interconnects electrically coupled to the I/O system to electrically connect the first and second chips to the I/O system. Each of the plurality of metal interconnects extends through a respective via to form a direct metallic connection with a metal interconnect on a neighboring re-distribution layer or a chip pad on the first or second chip.
摘要翻译：嵌入式芯片封装（ECP）包括在垂直方向上连接在一起的多个再分配层，以形成层叠叠层，每个再分布层具有形成在其中的通孔。嵌入式芯片封装还包括嵌入层压叠层中的第一芯片和附接到层压叠层并相对于第一芯片沿垂直方向堆叠的第二芯片，每个芯片具有多个芯片焊盘。嵌入式芯片封装进一步包括位于叠层堆叠的最外层再分布层上的输入/输出（I / O）系统和电耦合到I / O系统的多个金属互连，以电连接第一和第二个芯片到I / O系统。多个金属互连件中的每一个延伸通过相应的通孔，以形成与第一或第二芯片上的相邻再分配层或芯片焊盘上的金属互连件的直接金属连接。

9. 发明申请

US20100133683A1 SYSTEM AND APPARATUS FOR VENTING ELECTRONIC PACKAGES AND METHOD OF MAKING SAME 有权
标题翻译：用于展示电子包的系统和装置及其制造方法
公开(公告)号：US20100133683A1
公开(公告)日：2010-06-03
申请号：US12326202
申请日：2008-12-02
申请人： Raymond Albert Fillion , Kevin M. Durocher , Elizabeth A. Burke , Thomas Bert Gorczyca , Charles G. Woychik
发明人： Raymond Albert Fillion , Kevin M. Durocher , Elizabeth A. Burke , Thomas Bert Gorczyca , Charles G. Woychik
IPC分类号： H01L23/34 , H01L23/00 , H01L21/02
CPC分类号： H01L23/49822 , H01L23/16 , H01L23/3128 , H01L23/49816 , H01L23/564 , H01L24/19 , H01L24/24 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05568 , H01L2224/05573 , H01L2224/12105 , H01L2924/00014 , H01L2924/01029 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/1461 , H01L2924/18162 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers.
摘要翻译：一种装置和方法，所述装置包括被配置为支撑多个电介质层的基板，位于所述基板中的装置耦合区域以及穿过所述基板形成的多个气体出口孔。多个气体出口孔被配置为提供湿气和脱气材料中的至少一种的排气，并且装置联接区域被配置为接收可耦合到多个电介质层的电子装置。

10. 发明授权

US08008781B2 Apparatus and method for reducing pitch in an integrated circuit 有权
标题翻译：用于降低集成电路中的音调的装置和方法
公开(公告)号：US08008781B2
公开(公告)日：2011-08-30
申请号：US12326214
申请日：2008-12-02
申请人： Raymond Albert Fillion , Kevin M. Durocher , Richard Joseph Saia , Paul Alan McConnelee
发明人： Raymond Albert Fillion , Kevin M. Durocher , Richard Joseph Saia , Paul Alan McConnelee
IPC分类号： H01L23/48
CPC分类号： H01L24/82 , H01L21/76804 , H01L21/76816 , H01L23/3114 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/92144 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/19042 , Y10T29/49155
摘要： An apparatus and method, the apparatus includes an electronic chip package including an electronic chip having a first contact pad and a second contact pad thereon and being free of an intervening contact pad therebetween, a first dielectric layer coupled to the electronic chip over the first and second contact pads, and a second dielectric layer coupled to the first dielectric layer such that a dielectric layer boundary is formed therebetween. The first dielectric layer has a first contact pad via formed therethrough at a first location corresponding to the first contact pad and extending down thereto. The second dielectric layer has a second contact pad via formed therethrough at a second location corresponding to the second contact pad and extending down thereto such that a second contact pad multi-layer via is formed through the first and second dielectric layers at the second location corresponding to the second contact pad.
摘要翻译：一种装置和方法，该装置包括电子芯片封装，其包括电子芯片，该电子芯片具有第一接触焊盘和第二接触焊盘，并且在其之间没有中间接触焊盘，第一介电层在第一和第二接触焊盘上耦合到电子芯片，第二接触焊盘和耦合到第一介电层的第二介电层，使得在它们之间形成介电层边界。第一电介质层具有在对应于第一接触焊盘并向下延伸的第一位置处穿过其形成的第一接触焊盘通孔。第二电介质层具有在对应于第二接触焊盘并向下延伸的第二位置处穿过其形成的第二接触焊盘通孔，使得在第二位置处形成第二接触焊盘多层通孔，所述第二接触焊盘多层通孔穿过第一和第二电介质层，到第二接触垫。

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