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1. 发明授权

US06477482B1 Power button controlled diagnostic mode for an information appliance 有权
标题翻译：用于信息设备的电源按钮控制诊断模式
公开(公告)号：US06477482B1
公开(公告)日：2002-11-05
申请号：US09542745
申请日：2000-04-04
申请人： Patrick E. Maupin , David F. Tobias
发明人： Patrick E. Maupin , David F. Tobias
IPC分类号： G06F1310
CPC分类号： G06F11/2284
摘要： A system adds functionality to a power button where use of the power button controls the entry and exit from a diagnostic mode. The system includes an information appliance connected to a diagnostic appliance. Once an information appliance is powered up, the information appliance monitors its power button for a press which indicates a request to enter a diagnostic mode. Absent a press of the power button, the system continues to be under control of the information appliance and never enters a diagnostic mode. However, if a press of the power button is detected, the system enters a diagnostic mode. Once in a diagnostic mode the system provides an exit therefrom by interpreting a power button press as a request to exit. The window of time to make such an exit closes once the diagnostic appliance achieves communication with the information appliance. If the power button is pressed during this window of time, then the system ends its diagnostic mode and control of the system returns to the information appliance. If the power button is pressed after the window of time has closed, then the diagnostic appliance retains control of the information appliance and maintains its ability to execute diagnostic type commands thereon. The illustrative system is particularly useful when incorporated into devices with limited interface connections such as legacy-free information appliances. The system allows for a standard existing button on the information appliance to serve diagnostic purposes, avoiding the need for initializing peripherals requiring substantial execution space.
摘要翻译：系统将功能添加到电源按钮，使用电源按钮控制进入并退出诊断模式。该系统包括连接到诊断设备的信息设备。一旦信息设备通电，信息设备就会监视其按钮的电源按钮，指示进入诊断模式的请求。没有按下电源按钮，系统继续受到信息设备的控制，并且不会进入诊断模式。但是，如果检测到按下电源按钮，系统进入诊断模式。一旦进入诊断模式，系统通过解释电源按钮按钮作为退出请求来提供退出。一旦诊断设备实现与信息设备的通信，进行此类退出的时间窗口就会关闭。如果在此窗口内按下电源按钮，系统将结束其诊断模式，系统的控制返回到信息设备。如果在时间窗口关闭后按下电源按钮，则诊断设备保持对信息设备的控制，并保持其在其上执行诊断类型命令的能力。当被并入具有有限接口连接的设备（例如无遗留信息设备）中时，说明性系统特别有用。该系统允许信息设备上的标准现有按钮用于诊断目的，避免需要初始化需要大量执行空间的外设。

2. 发明授权

US6145103A Emulator support mode for disabling and reconfiguring timeouts of a watchdog timer 失效
标题翻译：仿真器支持模式，用于禁用和重新配置看门狗定时器的超时
公开(公告)号：US6145103A
公开(公告)日：2000-11-07
申请号：US56509
申请日：1998-04-07
申请人： Melanie D. Typaldos , Patrick E. Maupin
发明人： Melanie D. Typaldos , Patrick E. Maupin
IPC分类号： G06F11/36 , G06F11/00
CPC分类号： G06F11/3648
摘要： A microcontroller-based device according to the present invention provides a watchdog timer having an emulator support mode for disabling and reconfiguring time-outs. When the watchdog timer is placed in the emulator support mode, the watchdog timer is inhibited from counting. In a disclosed embodiment, the watchdog timer is inhibited from counting by deasserting a count enable signal. A watchdog time-out is thus prevented from occurring during the emulator support mode. Also, during the emulator support mode, the watchdog timer control register is writable, allowing the emulator to disable a watchdog timer, enable the timer, or program a new time-out value for the timer. The watchdog timer control register is writable regardless of the state of the enable bit of the timer. Further, in the emulator support mode, a watchdog timer current count becomes readable and writable at a predetermined register address above the watchdog timer control register subsequent to a write of a write key sequence to the watchdog timer control register. By writing and reading the predetermined register address location, the emulator is able to define and monitor a condition as the watchdog timer is approaching its timeout value. By monitoring a condition as the watchdog timer approaches its timeout value, a software debugger may better predict and appreciate the behavior of a microcontroller-based device prior to a watchdog time-out. In a disclosed embodiment, the watchdog timer current count is readable and writable through a watchdog timer count high register and a watchdog timer count low register.
摘要翻译：根据本发明的基于微控制器的设备提供具有用于禁用和重新配置超时的仿真器支持模式的看门狗定时器。看门狗定时器处于仿真器支持模式时，看门狗定时器被禁止计数。在公开的实施例中，通过使计数使能信号无效来禁止看门狗定时器计数。因此，在仿真器支持模式期间可以防止发生看门狗超时。此外，在仿真器支持模式下，看门狗定时器控制寄存器是可写的，允许仿真器禁用看门狗定时器，使能定时器或为定时器编程新的超时值。无论定时器的使能位的状态如何，看门狗定时器控制寄存器都是可写的。此外，在仿真器支持模式下，在写入键序列写入看门狗定时器控制寄存器之后，看门狗定时器当前计数在看门狗定时器控制寄存器之上的预定寄存器地址处可读写。通过写入和读取预定的寄存器地址位置，仿真器能够定义和监视看门狗定时器接近其超时值的条件。通过在看门狗定时器接近其超时值时监视条件，软件调试器可以在看门狗超时之前更好地预测和理解基于微控制器的器件的行为。在公开的实施例中，通过看门狗定时器计数高位寄存器和看门狗定时器计数低寄存器，看门狗定时器当前计数是可读写的。

3. 发明授权

US5958024A System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver 失效
标题翻译：具有接收数据寄存器的系统，用于存储指示异步串行接收器的状态的帧和状态位的至少九个数据位
公开(公告)号：US5958024A
公开(公告)日：1999-09-28
申请号：US920930
申请日：1997-08-29
申请人： Melanie D. Typaldos , Patrick E. Maupin
发明人： Melanie D. Typaldos , Patrick E. Maupin
IPC分类号： G06F13/38 , G06F13/28 , G06F13/42
CPC分类号： G06F13/385
摘要： An asynchronous serial port having a control register and at least one data register exchanges data with a serial bus. The asynchronous serial port includes an indicator representing whether the data register contains all of the data bits, or whether some of the data may be stored in the control register. When a nine-bit data source (or any data source having more than eight bits of data) is received, the bits need not be divided among multiple registers, but can all be stored in the receive-data register. This is particularly useful during DMA or when the exchange of data has been suspended, for example by an interrupt, while additional frames may be received by the asynchronous serial port. Because frames are stored in a single register when an extended write bit or an extended read bit is set. Further, the receive data register also stores status bits associated with received data. This is especially useful during DMA operations, when status, including parity, frame, or overrun errors can be associated with a particular data item examining the stored DMA data itself.
摘要翻译：具有控制寄存器和至少一个数据寄存器的异步串口与串行总线交换数据。异步串行端口包括表示数据寄存器是否包含所有数据位的指示器，还是一些数据可能存储在控制寄存器中。当接收到9位数据源（或具有多于8位数据的数据源）时，这些位不需要在多个寄存器之间划分，而是可以全部存储在接收数据寄存器中。这在DMA期间或者当数据交换已被暂停时（例如通过中断）特别有用，而异步串行端口可以接收附加帧。因为当扩展写位或扩展读位置1时，帧存储在单个寄存器中。此外，接收数据寄存器还存储与接收数据相关联的状态位。这在DMA操作中特别有用，当状态（包括奇偶校验，帧或超限错误）可以与检查存储的DMA数据本身的特定数据项相关联时。

4. 发明授权

US06212593B1 Method and apparatus for generating interrupts on a buffer by buffer basis in buffer descriptor ring direct memory access system 失效
标题翻译：用于在缓冲器描述符环直接存储器访问系统中通过缓冲器在缓冲器上产生中断的方法和装置
公开(公告)号：US06212593B1
公开(公告)日：2001-04-03
申请号：US09088478
申请日：1998-06-01
申请人： Thai H. Pham , Patrick E. Maupin
发明人： Thai H. Pham , Patrick E. Maupin
IPC分类号： G06F1314
CPC分类号： G06F13/32
摘要： A microcontroller implements a buffer descriptor ring direct memory access (DMA) unit that can transmit a chained series of buffers without processor intervention. The buffers, however, include an interrupt on end-of-buffer flag that allows for an interrupt to be generated at the end of each buffer on a buffer-by-buffer basis.
摘要翻译：微控制器实现缓冲描述符环直接存储器访问（DMA）单元，其可以在没有处理器干预的情况下传输链接的一系列缓冲器。然而，缓冲区包括缓冲区结束标志上的中断，允许在逐个缓冲器的基础上在每个缓冲区的末尾生成一个中断。

5. 发明授权

US06327259B1 Flexible placement of serial data within a time divisioned multiplexed frame through programmable time slot start and stop bit positions 失效
标题翻译：通过可编程时隙开始和停止位位置，在时分复用帧内灵活放置串行数据
公开(公告)号：US06327259B1
公开(公告)日：2001-12-04
申请号：US09088788
申请日：1998-06-01
申请人： Kenny Kok-Hoong Chiu , Eric G. Chambers , Patrick E. Maupin
发明人： Kenny Kok-Hoong Chiu , Eric G. Chambers , Patrick E. Maupin
IPC分类号： H04J300
CPC分类号： G06F13/372 , H04J3/0605 , H04J3/1682
摘要： A microcontroller is provided with one or more synchronous serial channels, such as HDLC channels, that are coupled to time slot assigners for communication over a time division multiplex bus. The time slot assigners each include a bit position start register and a bit position stop register that allows the time slot assigner to enable and disable the associated synchronous serial channel on the arrival of a specific bit position within the time division multiplex bus frame. Further, an end of slot adjust register provides for additional bits to be placed by the time slot assigner on to the end of a slot that is transmitted by an associated synchronous serial communication channel transmitter.
摘要翻译：微控制器被提供有一个或多个同步串行通道，例如HDLC通道，其耦合到时隙分配器，用于通过时分复用总线进行通信。时隙分配器各自包括位位置开始寄存器和位位置停止寄存器，其允许时隙分配器在时分多路复用总线帧中的特定位位置到达时启用和禁用相关联的同步串行通道。此外，时隙调整寄存器的结尾提供由时隙分配器放置到相关联的同步串行通信信道发射机发送的时隙的末端的附加比特。

6. 发明授权

US6154832A Processor employing multiple register sets to eliminate interrupts 有权
标题翻译：处理器采用多个寄存器组来消除中断
公开(公告)号：US6154832A
公开(公告)日：2000-11-28
申请号：US205444
申请日：1998-12-04
申请人： Patrick E. Maupin
发明人： Patrick E. Maupin
IPC分类号： G06F9/30 , G06F9/48 , H04L12/40 , H04L12/64 , G06F9/312
CPC分类号： G06F9/4812 , G06F9/30123 , H04L12/40123
摘要： A processor includes multiple register sets. A different register set may be dedicated to each of one or more interrupt sources, and yet another register set may be dedicated to other (non-interrupt) tasks. The interrupt sources may record interrupt service requests instead of signalling an interrupt to the processor. Periodically, the processor may poll the interrupt sources to determine if a service request is recorded.
摘要翻译：处理器包括多个寄存器组。一个不同的寄存器组可专用于一个或多个中断源中的每一个，并且另一个寄存器组可专用于其他（非中断）任务。中断源可以记录中断服务请求，而不是向处理器发出中断信号。周期性地，处理器可以轮询中断源以确定是否记录服务请求。

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