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1. 发明授权

US4676867A Planarization process for double metal MOS using spin-on glass as a sacrificial layer 失效
标题翻译：使用旋涂玻璃作为牺牲层的双金属MOS的平面化工艺
公开(公告)号：US4676867A
公开(公告)日：1987-06-30
申请号：US871655
申请日：1986-06-06
申请人： Patricia C. Elkins , Yau-Wai D. Chan , Keh-Fei C. Chi , Karen A. Reinhardt , Rebecca Y. Tang , Robert L. Zwingman
发明人： Patricia C. Elkins , Yau-Wai D. Chan , Keh-Fei C. Chi , Karen A. Reinhardt , Rebecca Y. Tang , Robert L. Zwingman
IPC分类号： H01L21/00 , H01L21/3105 , H01L21/311 , H01L21/768 , B44C1/22 , C03C15/00 , C03C25/06 , C23F1/02
CPC分类号： H01L21/76886 , H01L21/31055 , H01L21/31116 , H01L21/76819
摘要： A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.

2. 发明授权

US5330930A Formation of vertical polysilicon resistor having a nitride sidewall for small static RAM cell 失效
标题翻译：形成具有用于小静态RAM单元的氮化物侧壁的垂直多晶硅电阻器
公开(公告)号：US5330930A
公开(公告)日：1994-07-19
申请号：US999745
申请日：1992-12-31
申请人： Keh-Fei C. Chi
发明人： Keh-Fei C. Chi
IPC分类号： H01L21/02 , H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L28/20 , H01L27/11 , H01L27/1112
摘要： A new method of forming a polysilicon resistor is achieved. Polysilicon gate structures and source/drain regions are formed in and on a semiconductor substrate. A passivation layer is formed overlying the gate structures. A contact window is opened to the drain portion of the source/drain region. A resistor is formed within the contact window as follows. A nitride layer is deposited over the passivation layer and within the contact window. The nitride layer is etched back to form nitride sidewalls within the contact window. A layer of polysilicon is deposited over the passivation layer and within the contact window. The polysilicon layer is etched back to leave the polysilicon only within the contact opening completing formation of the resistor. A second contact window is opened to the source portion of the source/drain region. A barrier metal layer is deposited over the passivation layer, over the resistor, and within the second contact window. A metal layer is deposited over the barrier metal layer and the metal interconnection of the integrated circuit is completed.
摘要翻译：实现了形成多晶硅电阻器的新方法。多晶硅栅极结构和源/漏区形成在半导体衬底中和之上。形成覆盖栅极结构的钝化层。接触窗口向源极/漏极区域的漏极部分开放。在接触窗内形成电阻器如下。氮化物层沉积在钝化层上方和接触窗内。蚀刻氮化物层以在接触窗内形成氮化物侧壁。一层多晶硅沉积在钝化层上和接触窗内。多晶硅层被回蚀刻以仅在接触开口内离开多晶硅，完成电阻器的形成。第二接触窗口向源极/漏极区域的源极部分开放。阻挡金属层沉积在钝化层上方，电阻上方，并在第二接触窗内。金属层沉积在阻挡金属层上，并且集成电路的金属互连完成。

3. 发明授权

US5543350A SRAM resistor tab doping by plug implant from buried contact 失效
标题翻译： SRAM电阻片通过埋入触点的插头植入物进行掺杂
公开(公告)号：US5543350A
公开(公告)日：1996-08-06
申请号：US536857
申请日：1995-09-29
申请人： Keh-Fei C. Chi , Seah K. Suan , Ling H. Yow
发明人： Keh-Fei C. Chi , Seah K. Suan , Ling H. Yow
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L27/1112
摘要： A new method of forming a back diffused resistive load element is achieved. A pattern of gate electrodes and interconnection lines is formed overlying a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate. An interpoly oxide layer is deposited overlying the top surfaces of the semiconductor substrate and etched away where it is not covered by a mask to provide an opening to a drain region within the semiconductor substrate and exposing a portion of a gate electrode wherein a spacer comprising interpoly oxide is left on the sidewall of the exposed gate electrode within the opening. In order to remove the interpoly oxide spacer, the interpoly oxide layer is overetched whereby the top portion of the drain region in the semiconductor substrate is etched away along with a portion of the dopant. First ions are implanted into the drain region and the exposed portion of the gate electrode. A third layer of undoped polysilicon is deposited over the surface of the interpoly oxide and within the opening and patterned. During subsequent processing, the first ions implanted into the drain region and the exposed portion of the gate electrode diffuse into the third layer of polysilicon and into the substrate increasing the drain junction depth. The third polysilicon layer forms the resistive load element. Second ions are implanted into the third polysilicon layer to define a resistor value.
摘要翻译：实现形成背扩散电阻性负载元件的新方法。在半导体衬底上形成栅电极和互连线的图案。源极和漏极区域形成在半导体衬底内。沉积叠层氧化物层，覆盖在半导体衬底的顶表面上并被蚀刻掉，其中未被掩模覆盖，以提供半导体衬底内的漏极区域的开口并露出栅电极的一部分，其中间隔物包括互补氧化物留在开口内的暴露的栅电极的侧壁上。为了去除多晶氧化物间隔物，将内部氧化物层进行蚀刻，由此半导体衬底中的漏极区域的顶部与掺杂剂的一部分一起被蚀刻掉。第一离子注入到漏极区域和栅电极的暴露部分中。未掺杂多晶硅的第三层沉积在多晶氧化物的表面上并且在开口内并被图案化。在随后的处理过程中，注入到漏极区域中的第一离子和栅电极的暴露部分扩散到第三层多晶硅中并进入衬底，增加漏极结深度。第三多晶硅层形成电阻性负载元件。将第二离子注入到第三多晶硅层中以限定电阻值。

4. 发明授权

US4639142A Dimension monitoring technique for semiconductor fabrication 失效
标题翻译：半导体制造尺寸监测技术
公开(公告)号：US4639142A
公开(公告)日：1987-01-27
申请号：US484666
申请日：1983-04-13
申请人： Pei-Ming D. Chow , Keh-Fei C. Chi
发明人： Pei-Ming D. Chow , Keh-Fei C. Chi
IPC分类号： H01L21/30 , G01B11/02 , H01L21/027 , H01L21/306 , H01L21/66 , G01B11/00
CPC分类号： G01B11/02
摘要： A method of visually monitoring the change in dimensions of elements on a surface of a semiconductor body during processing is provided. A fixed pattern of scale images on the surface with a predetermined distance between images, together with a wedge-shaped element is provided on the surface. The wedge element has an apex adjacent one of the images and extends in a direction along other ones of the images. The semiconductor body is processed and the dimensions of the wedge-shaped element (as well as the scale image) change. One may then subsequently visually inspect the wedge shaped element with respect to the pattern of images to determine the extent of the change in dimension of the wedge shaped element during processing.
摘要翻译：提供了一种在处理期间可视地监测半导体本体表面上的元件的尺寸变化的方法。表面上具有在图像之间具有预定距离的表面上的固定图案的鳞片图像以及楔形元件。楔形元件具有与图像之一相邻的顶点并且沿着沿其他图像的方向延伸。处理半导体本体，并且楔形元件（以及刻度图像）的尺寸改变。然后可以随后相对于图像图案目视检查楔形元件，以确定楔形元件在处理期间的尺寸变化的程度。

5. 发明授权

US5208181A Locos isolation scheme for small geometry or high voltage circuit 失效
标题翻译：小几何或高压电路的Locos隔离方案
公开(公告)号：US5208181A
公开(公告)日：1993-05-04
申请号：US930367
申请日：1992-08-17
申请人： Keh-Fei C. Chi
发明人： Keh-Fei C. Chi
IPC分类号： H01L21/266 , H01L21/32 , H01L21/762
CPC分类号： H01L21/266 , H01L21/32 , H01L21/76216 , Y10S438/944
摘要： A process and for fabricating field oxide isolation pattern with field implants associated therewith that can be used for increasingly smaller dimensional elements, for example in feature sizes of 0.8 micrometers or less, and simpler processing than the prior art is described. A semiconductor substrate is provided. A multilayer oxidation masking structure of a thin silicon oxide layer, a silicon nitride layer, and a polycrystalline silicon layer is formed. The multilayer oxidation mask is patterned by removing the silicon nitride layer and the polycrystalline silicon layer from the areas designated to have field oxide isolation grown therein to form a narrow opening. The structure is exposed to an oxidizing environment such that the polysilicon oxide layer forms an "overhang" over part of the field isolation region. Ion implanting in a vertical direction is accomplished to form the field implant in the silicon surface of the dimension of the narrow opening less the overhang. The polysilicon oxide layer is removed. The field oxide insulator structure is grown by subjecting the structure to oxidation whereby the field implant is confined under the field oxide isolation and not encroaching the planned source/drain implant regions.
摘要翻译：描述了一种用于制造具有与其相关的场植入物的场氧化物隔离图案的方法，其可以用于越来越小的尺寸元件，例如在0.8微米或更小的特征尺寸中，并且比现有技术更简单的处理。提供半导体衬底。形成薄氧化硅层，氮化硅层和多晶硅层的多层氧化掩模结构。通过从指定为在其中生长的场氧化物隔离的区域去除氮化硅层和多晶硅层来形成多层氧化掩模以形成窄开口。该结构暴露于氧化环境，使得多晶硅氧化物层在场隔离区域的一部分上形成“突出”。实现在垂直方向上的离子注入，以在狭窄开口的尺寸的硅表面中形成野外注入，而不是悬垂。去除多晶硅氧化物层。通过对结构进行氧化来生长场氧化物绝缘体结构，由此场场注入被限制在场氧化物隔离之下，而不会侵占规划的源/漏注入区。

6. 发明授权

US5173437A Double polysilicon capacitor formation compatable with submicron processing 失效
标题翻译：双晶硅电容器形成与亚微米加工相容
公开(公告)号：US5173437A
公开(公告)日：1992-12-22
申请号：US739222
申请日：1991-08-01
申请人： Keh-Fei C. Chi
发明人： Keh-Fei C. Chi
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： A method for fabricating an integrated circuit having a double polysilicon capacitors and metal oxide silicon field effect devices which are compatible to one micrometer or less processing is described. First, a pattern of recessed oxide isolation is formed on the surface of a silicon substrate. The pattern separates surface regions of silicon from other such regions. A gate dielectric layer is formed on the surface of surface regions of the silicon with a suitable dopant concentration. A first polysilicon layer is formed over the gate dielectric layer and over the field oxide having a suitable doping concentration. An interpoly dielectric layer is formed over the surface of the first polysilicon layer. A second poly silicon layer is formed over the interpoly dielectric layer having a suitable doping concentration. The second polysilicon layer is patterned using a first resist masking and suitable etching to leave only the top plate of the capacitor in the second polysilicon layer. The interpoly dielectric layer is removed except where it is located beneath the top plate by using top plate of the capacitor in second polysilicon layer as the etching mask. The first polysilicon layer is now patterned using a second resist masking and suitable etching to leave only the bottom plate of the capacitor and the gate electrode of the transistor in the first polysilicon layer. The second resist masking layer is removed. The elements of the integrated circuit are completed by conventional processing.
摘要翻译：描述了具有兼容于一微米或更小的处理的双重多晶硅电容器和金属氧化物硅场效应器件的集成电路的制造方法。首先，在硅衬底的表面上形成凹陷氧化物隔离图案。该图案将硅的表面区域与其它这样的区域分离。在具有合适的掺杂剂浓度的硅的表面区域的表面上形成栅极电介质层。第一多晶硅层形成在栅极电介质层上方并且在具有合适掺杂浓度的场氧化物上。在第一多晶硅层的表面上形成多层介电层。第二多晶硅层形成在具有合适掺杂浓度的多晶硅电介质层上。使用第一抗蚀剂掩模和合适的蚀刻将第二多晶硅层图案化，以仅留下第二多晶硅层中的电容器的顶板。通过使用第二多晶硅层中的电容器的顶板作为蚀刻掩模，除去其间位于顶板下方的多层电介质层。现在使用第二抗蚀剂掩模和合适的蚀刻将第一多晶硅层图案化，仅留下第一多晶硅层中的电容器的底板和晶体管的栅电极。去除第二抗蚀剂掩模层。集成电路的元件通过常规处理完成。

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