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1. 发明授权

US5543350A SRAM resistor tab doping by plug implant from buried contact 失效
标题翻译： SRAM电阻片通过埋入触点的插头植入物进行掺杂
公开(公告)号：US5543350A
公开(公告)日：1996-08-06
申请号：US536857
申请日：1995-09-29
申请人： Keh-Fei C. Chi , Seah K. Suan , Ling H. Yow
发明人： Keh-Fei C. Chi , Seah K. Suan , Ling H. Yow
IPC分类号： H01L21/8244 , H01L27/11 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L27/1112
摘要： A new method of forming a back diffused resistive load element is achieved. A pattern of gate electrodes and interconnection lines is formed overlying a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate. An interpoly oxide layer is deposited overlying the top surfaces of the semiconductor substrate and etched away where it is not covered by a mask to provide an opening to a drain region within the semiconductor substrate and exposing a portion of a gate electrode wherein a spacer comprising interpoly oxide is left on the sidewall of the exposed gate electrode within the opening. In order to remove the interpoly oxide spacer, the interpoly oxide layer is overetched whereby the top portion of the drain region in the semiconductor substrate is etched away along with a portion of the dopant. First ions are implanted into the drain region and the exposed portion of the gate electrode. A third layer of undoped polysilicon is deposited over the surface of the interpoly oxide and within the opening and patterned. During subsequent processing, the first ions implanted into the drain region and the exposed portion of the gate electrode diffuse into the third layer of polysilicon and into the substrate increasing the drain junction depth. The third polysilicon layer forms the resistive load element. Second ions are implanted into the third polysilicon layer to define a resistor value.
摘要翻译：实现形成背扩散电阻性负载元件的新方法。在半导体衬底上形成栅电极和互连线的图案。源极和漏极区域形成在半导体衬底内。沉积叠层氧化物层，覆盖在半导体衬底的顶表面上并被蚀刻掉，其中未被掩模覆盖，以提供半导体衬底内的漏极区域的开口并露出栅电极的一部分，其中间隔物包括互补氧化物留在开口内的暴露的栅电极的侧壁上。为了去除多晶氧化物间隔物，将内部氧化物层进行蚀刻，由此半导体衬底中的漏极区域的顶部与掺杂剂的一部分一起被蚀刻掉。第一离子注入到漏极区域和栅电极的暴露部分中。未掺杂多晶硅的第三层沉积在多晶氧化物的表面上并且在开口内并被图案化。在随后的处理过程中，注入到漏极区域中的第一离子和栅电极的暴露部分扩散到第三层多晶硅中并进入衬底，增加漏极结深度。第三多晶硅层形成电阻性负载元件。将第二离子注入到第三多晶硅层中以限定电阻值。

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