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1. 发明申请

US20140189311A1 SYSTEM AND METHOD FOR PERFORMING A SHUFFLE INSTRUCTION 审中-公开
标题翻译：用于执行小指令的系统和方法
公开(公告)号：US20140189311A1
公开(公告)日：2014-07-03
申请号：US13732243
申请日：2012-12-31
申请人： Patrice Roussel , Srinivas Chennupaty , Michael Cranford , Mohammad Abdallah , James Coke , Katherine Kong
发明人： Patrice Roussel , Srinivas Chennupaty , Michael Cranford , Mohammad Abdallah , James Coke , Katherine Kong
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032
摘要： An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
摘要翻译：描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。具有至少两个数据元素的第二压缩数据操作数被访问。第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。

2. 发明授权

US6041404A Dual function system and method for shuffling packed data elements 失效
公开(公告)号：US6041404A
公开(公告)日：2000-03-21
申请号：US52996
申请日：1998-03-31
申请人： Patrice Roussel , Srinivas Chennupaty , Mike Cranford , Mohammad Abdallah , Jim Coke , Katherine Kong
发明人： Patrice Roussel , Srinivas Chennupaty , Mike Cranford , Mohammad Abdallah , Jim Coke , Katherine Kong
IPC分类号： G06F9/30 , G06F9/315 , G06F9/15
CPC分类号： G06F15/7885 , G06F9/30025 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.

3. 再颁专利

USRE45458E1 Dual function system and method for shuffling packed data elements 有权
标题翻译：用于混合打包数据元素的双功能系统和方法
公开(公告)号：USRE45458E1
公开(公告)日：2015-04-07
申请号：US10104205
申请日：2002-03-21
申请人： Patrice Roussel , Srinivas Chennupaty , Micheal D. Cranford , Mohammed A. Abdallah , James Coke , Katherine Kong
发明人： Patrice Roussel , Srinivas Chennupaty , Micheal D. Cranford , Mohammed A. Abdallah , James Coke , Katherine Kong
IPC分类号： G06F9/315 , G06F15/78
CPC分类号： G06F15/7885 , G06F9/30025 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
摘要翻译：描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。具有至少两个数据元素的第二压缩数据操作数被访问。第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。

4. 发明授权

US06970994B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06970994B2
公开(公告)日：2005-11-29
申请号：US09852217
申请日：2001-05-08
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.
摘要翻译：讨论了用于执行部分宽度打包数据指令的方法和装置。处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相比之下，第二组指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

5. 发明申请

US20050216706A1 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US20050216706A1
公开(公告)日：2005-09-29
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

6. 发明授权

US07467286B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US07467286B2
公开(公告)日：2008-12-16
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H04Q3/00
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

7. 发明授权

US6122725A Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US6122725A
公开(公告)日：2000-09-19
申请号：US53002
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30181 , G06F9/30185 , G06F9/30196
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元和耦合到寄存器重命名单元的解码器。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为对构造寄存器文件中的每个指定一个或多个寄存器的第一和第二组指令（例如，一组全宽度压缩数据指令和一组部分宽度压缩数据指令）进行解码。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。

8. 发明申请

US20130013896A1 LOAD/MOVE AND DUPLICATE INSTRUCTIONS FOR A PROCESSOR 有权
标题翻译：处理器的负载/移动和双重指令
公开(公告)号：US20130013896A1
公开(公告)日：2013-01-10
申请号：US13620194
申请日：2012-09-14
申请人： Patrice Roussel
发明人： Patrice Roussel
IPC分类号： G06F9/30
CPC分类号： G06F9/3001 , G06F9/30032 , G06F9/30036 , G06F9/30043
摘要： A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.
摘要翻译：一种方法包括在处理器中将源的位的第一部分加载/移动到目的地寄存器的第一部分中，并且复制目的地寄存器的后续部分中的位的第一部分。

9. 发明授权

US06961845B2 System to perform horizontal additions 失效
标题翻译：系统执行水平添加
公开(公告)号：US06961845B2
公开(公告)日：2005-11-01
申请号：US10193645
申请日：2002-07-09
申请人： Patrice Roussel
发明人： Patrice Roussel
IPC分类号： G06F9/302
CPC分类号： G06F9/30036 , G06F9/3001
摘要： A method and apparatus for including in a processor instructions for performing intra-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the result of an intra-add operation on data elements in the first packed data.
摘要翻译：一种用于在处理器中包括用于对打包数据执行加入内操作的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包数据。处理器对第一打包数据中的数据元素执行操作，以响应于接收到指令而在第二打包数据中生成多个数据元素。第二打包数据中的多个数据元素中的至少两个存储第一打包数据中的数据元素的加入内操作的结果。

10. 发明授权

US06292815B1 Data conversion between floating point packed format and integer scalar format 失效
标题翻译：浮点打包格式与整数标量格式之间的数据转换
公开(公告)号：US06292815B1
公开(公告)日：2001-09-18
申请号：US09069796
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9302
CPC分类号： G06T1/20 , H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a scalar format. At least one of the numbers in the scalar format is converted to a number in the floating point format. The number in the floating point format is placed in a register of a second set of architectural registers in a packed format.
摘要翻译：描述用于在浮点格式和整数格式之间转换数字的方法和指令。数字以整数格式存储在标量格式的第一组架构寄存器的寄存器中。标量格式中的至少一个数字将以浮点格式转换为数字。浮点格式的数字以打包格式放置在第二组结构寄存器的寄存器中。

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