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1. 发明申请

US20140189311A1 SYSTEM AND METHOD FOR PERFORMING A SHUFFLE INSTRUCTION 审中-公开
标题翻译：用于执行小指令的系统和方法
公开(公告)号：US20140189311A1
公开(公告)日：2014-07-03
申请号：US13732243
申请日：2012-12-31
申请人： Patrice Roussel , Srinivas Chennupaty , Michael Cranford , Mohammad Abdallah , James Coke , Katherine Kong
发明人： Patrice Roussel , Srinivas Chennupaty , Michael Cranford , Mohammad Abdallah , James Coke , Katherine Kong
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30032
摘要： An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
摘要翻译：描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。具有至少两个数据元素的第二压缩数据操作数被访问。第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。

2. 再颁专利

USRE45458E1 Dual function system and method for shuffling packed data elements 有权
标题翻译：用于混合打包数据元素的双功能系统和方法
公开(公告)号：USRE45458E1
公开(公告)日：2015-04-07
申请号：US10104205
申请日：2002-03-21
申请人： Patrice Roussel , Srinivas Chennupaty , Micheal D. Cranford , Mohammed A. Abdallah , James Coke , Katherine Kong
发明人： Patrice Roussel , Srinivas Chennupaty , Micheal D. Cranford , Mohammed A. Abdallah , James Coke , Katherine Kong
IPC分类号： G06F9/315 , G06F15/78
CPC分类号： G06F15/7885 , G06F9/30025 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method for performing a shuffle operation on packed data using computer-implemented steps is described. In one embodiment, a first packed data operand having at least two data elements is accessed. A second packed data operand having at least two data elements is accessed. One of the data elements in the first packed data operand is shuffled into a lower destination field of a destination register, and one of the data elements in the second packed data operand is shuffled into an upper destination field of the destination register.
摘要翻译：描述了使用计算机实现的步骤对打包数据执行洗牌操作的装置和方法。在一个实施例中，访问具有至少两个数据元素的第一打包数据操作数。具有至少两个数据元素的第二压缩数据操作数被访问。第一打包数据操作数中的数据元素之一被混洗到目的地寄存器的较低目的地字段中，并且第二打包数据操作数中的数据元素中的一个被混洗到目的地寄存器的上目的地字段中。

3. 发明授权

US06970994B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06970994B2
公开(公告)日：2005-11-29
申请号：US09852217
申请日：2001-05-08
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.
摘要翻译：讨论了用于执行部分宽度打包数据指令的方法和装置。处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相比之下，第二组指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

4. 发明申请

US20050216706A1 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US20050216706A1
公开(公告)日：2005-09-29
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

5. 发明授权

US07467286B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US07467286B2
公开(公告)日：2008-12-16
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H04Q3/00
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

6. 发明授权

US6122725A Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US6122725A
公开(公告)日：2000-09-19
申请号：US53002
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Patrice Roussel , Ticky Thakkar , Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3822 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/3013 , G06F9/30145 , G06F9/30181 , G06F9/30185 , G06F9/30196
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元和耦合到寄存器重命名单元的解码器。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为对构造寄存器文件中的每个指定一个或多个寄存器的第一和第二组指令（例如，一组全宽度压缩数据指令和一组部分宽度压缩数据指令）进行解码。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。

7. 发明授权

US06192467B1 Executing partial-width packed data instructions 失效
公开(公告)号：US06192467B1
公开(公告)日：2001-02-20
申请号：US09053000
申请日：1998-03-31
申请人： Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
发明人： Mohammad A. Abdallah , Vladimir Pentkovski , James Coke
IPC分类号： G06F922
CPC分类号： G06F9/3017 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/3822 , G06F9/384
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.

8. 发明授权

US07430578B2 Method and apparatus for performing multiply-add operations on packed byte data 有权
标题翻译：对打包字节数据进行乘法运算的方法和装置
公开(公告)号：US07430578B2
公开(公告)日：2008-09-30
申请号：US10610831
申请日：2003-06-30
申请人： Eric Debes , William W. Macy , Jonathan J. Tyler , James Coke , Frank Binns , Scott Rodgers , Peter Ruscito , Bret Toll , Vesselin Naydenov , Masood Tahir , David Jackson
发明人： Eric Debes , William W. Macy , Jonathan J. Tyler , James Coke , Frank Binns , Scott Rodgers , Peter Ruscito , Bret Toll , Vesselin Naydenov , Masood Tahir , David Jackson
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F17/147 , G06F17/15
摘要： A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.
摘要翻译：一种用于在处理器中包括用于对压缩字节数据执行乘法运算的指令的方法和装置。在一个实施例中，处理器耦合到存储器。存储器中存储有第一打包字节数据和第二打包字节数据。处理器对所述第一打包字节数据和所述第二打包字节数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。该第三打包数据中的多个数据元素存储对第一和第二打包字节数据中的数据元素执行加法运算的结果。

9. 发明授权

US6026455A Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system 失效
标题翻译：用于为重试总线主机向计算机系统中连接两条总线的数据传输桥提供有保障的访问的架构和方法
公开(公告)号：US6026455A
公开(公告)日：2000-02-15
申请号：US201817
申请日：1994-02-24
申请人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
发明人： Nilesh Shah , James Coke , Jasmin Ajanovic , Dahmane Dahmani , Rajeev Prasad
IPC分类号： G06F13/40 , G06F13/36
CPC分类号： G06F13/4031
摘要： A bridge circuit adapted to be associated with a PCI and a secondary bus circuits which bridge circuit includes circuitry for storing an indication that a particular PCI bus master has attempted an access of the secondary bus and has been forced to retry that access, circuitry for masking any retry until the bus is again available, and circuitry for providing an interval during which a retrying PCI bus master is guaranteed access to the secondary bus in favor of a bus master on the secondary bus after the bus is relinquished so that a sequence of retry operations causing a loss of bandwidth on the PCI bus is not generated.
摘要翻译：适于与PCI和辅助总线电路相关联的桥接电路，桥接电路包括用于存储特定PCI总线主机尝试访问辅助总线并已被迫重试该接入的指示的电路，用于屏蔽的电路任何重试直到总线再次可用，以及用于提供间隔时间的电路，在该间隔期间，重试PCI总线主机被保证访问辅助总线，有利于在总线被放弃之后辅助总线上的总线主机，使得重试次序不会产生导致PCI总线带宽损失的操作。

10. 发明授权

US5455915A Computer system with bridge circuitry having input/output multiplexers and third direct unidirectional path for data transfer between buses operating at different rates 失效
标题翻译：具有桥接电路的计算机系统具有输入/输出多路复用器和第三直接单向路径，用于以不同速率工作的总线之间的数据传输
公开(公告)号：US5455915A
公开(公告)日：1995-10-03
申请号：US168765
申请日：1993-12-16
申请人： James Coke
发明人： James Coke
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/405
摘要： A bridge circuit adapted to be associated with a first and a second bus circuit which includes a first unidirectional path including a buffer for storing read data or addresses, a second unidirectional path including a buffer for storing write data or addresses, a third direct unidirectional path, an input circuit for multiplexing data or addresses from either of the first or second bus circuits, an output circuit for transferring data from any of the three unidirectional paths to either the first or the second bus circuit, and sources of signals for controlling the particular unidirectional path taken depending on the transfer operation being accomplished.
摘要翻译：一种适于与第一和第二总线电路相关联的桥接电路，其包括包括用于存储读取数据或地址的缓冲器的第一单向路径，包括用于存储写入数据或地址的缓冲器的第二单向路径，第三直接单向路径用于从第一或第二总线电路中的任一个复用数据或地址的输入电路，用于将数据从三个单向路径中的任何一个传送到第一或第二总线电路的输出电路，以及用于控制特定的信号的信号源取决于完成的传送操作的单向路径。

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