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1. 发明授权

US07512925B2 System and method for reducing test time for loading and executing an architecture verification program for a SoC 失效
标题翻译：用于减少加载和执行SoC架构验证程序的测试时间的系统和方法
公开(公告)号：US07512925B2
公开(公告)日：2009-03-31
申请号：US11457538
申请日：2006-07-14
申请人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V. N. Srinivas
发明人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V. N. Srinivas
IPC分类号： G06F17/50 , G01R31/28 , G01R31/38
CPC分类号： G01R31/318536
摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
摘要翻译：提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。

2. 发明申请

US20080034261A1 System and Method for Reducing Test Time for Loading and Executing an Architecture Verification Program for a Soc 失效
标题翻译：系统和方法，用于减少加载和执行体系结构验证程序的测试时间
公开(公告)号：US20080034261A1
公开(公告)日：2008-02-07
申请号：US11457538
申请日：2006-07-14
申请人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V.N. Srinivas
发明人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V.N. Srinivas
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
摘要翻译：提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。

3. 发明授权

US07711875B2 High speed on-chip serial link apparatus 有权
标题翻译：高速片上串行连接装置
公开(公告)号：US07711875B2
公开(公告)日：2010-05-04
申请号：US12013913
申请日：2008-01-14
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译：提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。因此，减少了本发明使用的复杂性和硅面积。该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

4. 发明申请

US20080133800A1 High Speed On-Chip Serial Link Apparatus 有权
标题翻译：高速片上串行链路设备
公开(公告)号：US20080133800A1
公开(公告)日：2008-06-05
申请号：US12013913
申请日：2008-01-14
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
IPC分类号： G06F1/12
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译：提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。因此，减少了本发明使用的复杂性和硅面积。该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

5. 发明授权

US07430624B2 High speed on-chip serial link apparatus and method 有权
标题翻译：高速片上串行连接装置及方法
公开(公告)号：US07430624B2
公开(公告)日：2008-09-30
申请号：US11242676
申请日：2005-10-04
申请人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
发明人： Tilman Gloekler , Ingemar Holm , Ralph C. Koester , Mack W. Riley
IPC分类号： G06F13/12 , G06F13/00
CPC分类号： G06F13/4054
摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.
摘要翻译：提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。因此，减少了本发明使用的复杂性和硅面积。该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

6. 发明授权

US08144689B2 Controlling asynchronous clock domains to perform synchronous operations 失效
标题翻译：控制异步时钟域执行同步操作
公开(公告)号：US08144689B2
公开(公告)日：2012-03-27
申请号：US12128315
申请日：2008-05-28
申请人： Nathan P. Chelstrom , Mack W. Riley
发明人： Nathan P. Chelstrom , Mack W. Riley
IPC分类号： H04L12/28
CPC分类号： G06F1/12 , H04J3/0638 , H04L7/005 , H04L7/02
摘要： A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of the functional elements of the chip are controlled by a synchronous clock so that the latches are controlled synchronously even across asynchronous boundaries of the chip. The synchronous operation may then be performed and the chip's functional elements returned to being controlled by a local clock in an asynchronous manner after completion of the synchronous operation. This synchronous operation may be, for example, a power on reset (POR) operation, a manufacturing test sequence, debug operation, or the like.
摘要翻译：提供了一种控制异步时钟域来执行同步操作的机制。利用该机制，当在芯片上执行同步操作时，芯片的功能元件的锁存器由同步时钟控制，使得锁存器甚至跨越芯片的异步边界同步地被控制。然后可以执行同步操作，并且在同步操作完成之后，芯片的功能元件以异步方式返回到由本地时钟控制。该同步操作可以是例如上电复位（POR）操作，制造测试序列，调试操作等。

7. 发明授权

US08027798B2 Digital thermal sensor test implementation without using main core voltage supply 失效
标题翻译：数字热传感器测试实现，不使用主芯电压供应
公开(公告)号：US08027798B2
公开(公告)日：2011-09-27
申请号：US11937134
申请日：2007-11-08
申请人： Charles R. Johns , Mack W. Riley , David W. Shan , Michael F. Wang
发明人： Charles R. Johns , Mack W. Riley , David W. Shan , Michael F. Wang
IPC分类号： G01C19/00 , G01K3/00 , H02H5/04
CPC分类号： G01K15/00 , G01K15/005
摘要： A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.
摘要翻译：提供了一种用于校准数字热传感器的方法和装置。具有多个数字热传感器的处理器芯片接收模拟电压。耦合到处理器芯片的测试电路接收时钟信号，耦合到测试电路的寄存器将每个时钟周期上的值输出到多个数字热传感器中的数字热传感器。数字热传感器响应于数字热传感器中接收的寄存器的值等于数字热传感器的温度阈值而转换输出状态。在转换点处的寄存器的值用于校准数字热传感器。响应于数字热敏传感器接收到的寄存器的值不能等于数字热传感器的温度阈值，增量器会在每个时钟周期内递增寄存器的值。

8. 发明授权

US07721168B2 eFuse programming data alignment verification 失效
标题翻译： eFuse编程数据对齐验证
公开(公告)号：US07721168B2
公开(公告)日：2010-05-18
申请号：US12202584
申请日：2008-09-02
申请人： Mack W. Riley
发明人： Mack W. Riley
IPC分类号： G01R31/3181 , G01R31/316
CPC分类号： G11C17/18
摘要： An eFuse data alignment verification mechanism is provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.
摘要翻译：提供eFuse数据对齐验证机制。对准锁存器被提供在写扫描链的一系列锁存单元中，并且逻辑单元耦合到对准锁存器。扫描到写入扫描链的一系列锁存单元中的数据序列优选地包括对准数据值。这些对准数据值被放置在数据序列内的位置，如果数据序列被适当地扫描到一系列锁存单元中，则使得数据值被存储在对准锁存器中。逻辑单元从对准锁存器接收数据信号，并确定数据值的正确模式是否存储在对准锁存器中。如果在对齐锁存器中存在适当的数据值模式，则对齐数据并将程序使能信号发送到eFuses库。

9. 发明申请

US20090083594A1 Testing Functional Boundary Logic at Asynchronous Clock Boundaries of an Integrated Circuit Device 有权
标题翻译：在集成电路器件的异步时钟边界上测试功能边界逻辑
公开(公告)号：US20090083594A1
公开(公告)日：2009-03-26
申请号：US12329030
申请日：2008-12-05
申请人： Nathan P. Chelstrom , Steven R. Ferguson , Mack W. Riley
发明人： Nathan P. Chelstrom , Steven R. Ferguson , Mack W. Riley
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318594 , G01R31/318558
摘要： Mechanisms for testing functional boundary logic at an asynchronous clock boundary of an integrated circuit device are provided. With these mechanisms, each clock domain has its own scan paths that do not cross domain boundaries. By eliminating the scanning across the boundaries, the requirement to have two clock grids in the asynchronously clocked domains may be eliminated. As a result, circuit area and design time with regard to the clock distribution design are reduced. In addition, removing the second clock grid, i.e. the high speed core or system clock, in the asynchronously clocked domains removes the requirement to have a multiplexing scheme for selection of clocking signals in the asynchronous domain. In addition to the above, the system and method provide boundary built-in-self-test logic for testing the functional crossing logic of boundaries between the clock domains in a functional mode of operation.
摘要翻译：提供了在集成电路器件的异步时钟边界处测试功能边界逻辑的机制。通过这些机制，每个时钟域都有自己的扫描路径，不会跨越域边界。通过消除跨越边界的扫描，可以消除在异步计时域中具有两个时钟网格的要求。结果，电路面积和时钟分配设计的设计时间缩短了。此外，在异步计时域中去除第二时钟网格，即高速核心或系统时钟，消除了在异步域中选择时钟信号的复用方案的要求。除了上述之外，系统和方法还提供了边界内置的自检逻辑，用于在功能操作模式下测试时钟域之间边界的功能交叉逻辑。

10. 发明申请

US20090055637A1 SECURE POWER-ON RESET ENGINE 失效
标题翻译：安全上电复位发动机
公开(公告)号：US20090055637A1
公开(公告)日：2009-02-26
申请号：US11844449
申请日：2007-08-24
申请人： Ingemar Holm , Ralph C. Koester , Cedric Lichtenau , Thomas Pflueger , Mack W. Riley
发明人： Ingemar Holm , Ralph C. Koester , Cedric Lichtenau , Thomas Pflueger , Mack W. Riley
IPC分类号： G06F15/177
CPC分类号： G06F21/575 , G06F21/71
摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.
摘要翻译：在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。

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