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1. 发明申请

US20070093999A1 Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component 有权
标题翻译：将虚拟信号导入电子测试设备，以方便电子元件的测试
公开(公告)号：US20070093999A1
公开(公告)日：2007-04-26
申请号：US11259315
申请日：2005-10-26
申请人： Parag Birmiwal , Robert Dixon , Hien Le , Kirk Morrow
发明人： Parag Birmiwal , Robert Dixon , Hien Le , Kirk Morrow
IPC分类号： G06F17/50
CPC分类号： G01R31/318364 , G01R31/318357
摘要： Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of: overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.
摘要翻译：通过方法，系统和程序产品促进电子元件验证测试，该产品允许从电子元件设计的模拟验证测试导出的虚拟信号输入到在实际电子元件的验证测试期间使用的电子测试设备。该方法包括：存储由电子元件设计的仿真测试得到的仿真数据; 采用电子测试设备对实际电子元件进行实时测试，并获得实时测试信号; 将存储的仿真数据与实际的实时测试信号自动相关; 以及执行以下至少之一：用所述实时测试信号叠加和/或显示所述相关仿真数据作为虚拟信号; 并根据所存储的模拟数据自动确定触发事件并触发电子测试设备，从而通过存储的仿真数据自动控制电子部件的实时测试。

2. 发明申请

US20080034261A1 System and Method for Reducing Test Time for Loading and Executing an Architecture Verification Program for a Soc 失效
标题翻译：系统和方法，用于减少加载和执行体系结构验证程序的测试时间
公开(公告)号：US20080034261A1
公开(公告)日：2008-02-07
申请号：US11457538
申请日：2006-07-14
申请人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V.N. Srinivas
发明人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V.N. Srinivas
IPC分类号： G01R31/28
CPC分类号： G01R31/318536
摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
摘要翻译：提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。

3. 发明申请

US20070220338A1 Method and system for generating checkpoints of hardware description language simulations that include a specific model state together with a software testcase state 审中-公开
标题翻译：用于生成硬件描述语言模拟的检查点的方法和系统，其包括具体的模型状态以及软件测试用例状态
公开(公告)号：US20070220338A1
公开(公告)日：2007-09-20
申请号：US11351233
申请日：2006-02-09
申请人： Parag Birmiwal , Tilman Gloekler , Srinivas Polisetty , Karl Uhl
发明人： Parag Birmiwal , Tilman Gloekler , Srinivas Polisetty , Karl Uhl
IPC分类号： G06F11/00
CPC分类号： G06F17/5022 , G06F11/3672
摘要： A method for performing verification is disclosed. In response to determining that a log replay module operating in a replay mode has received a command from a testcase that is not equal to a next command in a replay log, a determination is made whether the command is a create relay checkpoint command with a testcase parameter matching a model checkpoint file. In response to determining that the command from the testcase is the create replay checkpoint command with the testcase parameter matching the model checkpoint file, the model checkpoint file is loaded into the simulator, and one or more items of cycle information of the simulator are set to information corresponding to the model checkpoint file.
摘要翻译：公开了一种用于执行验证的方法。响应于确定以重放模式操作的日志重放模块已经从重放日志中不等于下一个命令的测试用例接收到命令，确定该命令是否是具有测试用例的创建中继检查点命令参数匹配模型检查点文件。响应于确定来自测试用例的命令是创建重放检查点命令，其中testcase参数与模型检查点文件匹配，模型检查点文件被加载到模拟器中，并且模拟器的一个或多个循环信息项被设置为对应于模型检查点文件的信息。

4. 发明授权

US08131906B2 Voltage indicator signal generation system and method 失效
标题翻译：电压指示信号发生系统及方法
公开(公告)号：US08131906B2
公开(公告)日：2012-03-06
申请号：US12963950
申请日：2010-12-09
申请人： Parag Birmiwal , Bernard Charles Drerup
发明人： Parag Birmiwal , Bernard Charles Drerup
IPC分类号： G06F13/36 , H05K7/10
CPC分类号： G06F13/4027
摘要： The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.
摘要翻译：本发明提供一种包括外围组件接口（PCI）主机桥的系统。 PCI主机桥被配置为耦合到PCI总线，并且接收系统复位信号，以基于接收到的系统复位信号产生PCI总线复位信号，以检测PCI总线的PCI操作模式，并且基于检测到的PCI操作模式生成电压指示器信号。电压调节器耦合到PCI主机桥，并被配置为接收电压指示器信号并且基于电压指示器信号来调节用于PCI总线的信令电压。

5. 发明申请

US20080195339A1 Performing Temporal Checking 有权
标题翻译：执行时间检查
公开(公告)号：US20080195339A1
公开(公告)日：2008-08-14
申请号：US12102510
申请日：2008-04-14
申请人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
发明人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
IPC分类号： G01R31/00
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译：公开了一种用于进行时间检查的装置。用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。在测试期间，信号记录器耦合到被测设备（DUT）。每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。每个计数模块与边缘检测模块之一相关联。每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

6. 发明申请

US20070136703A1 Method and apparatus for performing temporal checking 有权
标题翻译：执行时间检查的方法和装置
公开(公告)号：US20070136703A1
公开(公告)日：2007-06-14
申请号：US11297308
申请日：2005-12-08
申请人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
发明人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译：公开了一种用于进行时间检查的装置。用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。在测试期间，信号记录器耦合到被测设备（DUT）。每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。每个计数模块与边缘检测模块之一相关联。每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

7. 发明申请

US20110074386A1 VOLTAGE INDICATOR SIGNAL GENERATION SYSTEM AND METHOD 失效
标题翻译：电压指示器信号发生系统及方法
公开(公告)号：US20110074386A1
公开(公告)日：2011-03-31
申请号：US12963950
申请日：2010-12-09
申请人： Parag Birmiwal , Bernard Charles Drerup
发明人： Parag Birmiwal , Bernard Charles Drerup
IPC分类号： G01R19/00
CPC分类号： G06F13/4027
摘要： The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.
摘要翻译：本发明提供一种包括外围组件接口（PCI）主机桥的系统。 PCI主机桥被配置为耦合到PCI总线，并且接收系统复位信号，以基于接收到的系统复位信号产生PCI总线复位信号，以检测PCI总线的PCI操作模式，并且基于检测到的PCI操作模式生成电压指示器信号。电压调节器耦合到PCI主机桥，并被配置为接收电压指示器信号并且基于电压指示器信号来调节用于PCI总线的信令电压。

8. 发明授权

US07915884B2 Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component 有权
标题翻译：将虚拟信号导入电子测试设备，以方便电子元件的测试
公开(公告)号：US07915884B2
公开(公告)日：2011-03-29
申请号：US12128058
申请日：2008-05-28
申请人： Parag Birmiwal , Robert C. Dixon , Hien M. Le , Kirk E. Morrow
发明人： Parag Birmiwal , Robert C. Dixon , Hien M. Le , Kirk E. Morrow
IPC分类号： G01R23/16 , G06F17/50
CPC分类号： G01R31/318364 , G01R31/318357
摘要： Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.
摘要翻译：通过方法，系统和程序产品促进电子元件验证测试，该产品允许从电子元件设计的模拟验证测试导出的虚拟信号输入到在实际电子元件的验证测试期间使用的电子测试设备。该方法包括：存储由电子元件设计的仿真测试得到的仿真数据; 采用电子测试设备对实际电子元件进行实时测试，并获得实时测试信号; 将存储的仿真数据与实际的实时测试信号自动相关; 以及使用所述实时测试信号执行将所述相关模拟数据叠加和/或显示为虚拟信号中的至少一个; 并根据所存储的模拟数据自动确定触发事件并触发电子测试设备，从而通过存储的仿真数据自动控制电子部件的实时测试。

9. 发明授权

US07853420B2 Performing temporal checking 有权
标题翻译：执行时间检查
公开(公告)号：US07853420B2
公开(公告)日：2010-12-14
申请号：US12102510
申请日：2008-04-14
申请人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
发明人： Parag Birmiwal , Sundeep Chadha , Tilman Gloekler , Johannes Koesters
IPC分类号： G06F17/50
CPC分类号： G01R31/318357 , G01R31/318328
摘要： An apparatus for performing temporal checking is disclosed. A signal logger for performing temporal checking includes a group of edge detection modules and a group of counting modules. During testing, the signal logger is coupled to a device under testing (DUT). Each of the edge detection modules is capable of maintaining edge information after a state transition on a signal within the DUT has been detected. Each of the counting modules is associated with one of the edge detection modules. Each of the countering modules is capable of maintaining a clock cycle count information associated with a detected edge. After the testing has been completed, temporal checking information on a signal within the DUT can be obtained by reconstructing the edge information and the associated clock cycle count information of the signal collected during the test.
摘要翻译：公开了一种用于进行时间检查的装置。用于执行时间检查的信号记录器包括一组边缘检测模块和一组计数模块。在测试期间，信号记录器耦合到被测设备（DUT）。每个边缘检测模块能够在检测到DUT内的信号的状态转换之后保持边缘信息。每个计数模块与边缘检测模块之一相关联。每个对抗模块能够维持与检测到的边缘相关联的时钟周期计数信息。在测试完成之后，可以通过重建在测试期间收集的信号的边缘信息和相关联的时钟周期计数信息来获得DUT内的信号的时间检查信息。

10. 发明授权

US07512925B2 System and method for reducing test time for loading and executing an architecture verification program for a SoC 失效
标题翻译：用于减少加载和执行SoC架构验证程序的测试时间的系统和方法
公开(公告)号：US07512925B2
公开(公告)日：2009-03-31
申请号：US11457538
申请日：2006-07-14
申请人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V. N. Srinivas
发明人： Parag Birmiwal , Tilman Gloekler , Mack W. Riley , Devi Shanmugam , Polisetty V. N. Srinivas
IPC分类号： G06F17/50 , G01R31/28 , G01R31/38
CPC分类号： G01R31/318536
摘要： A system and method for reducing test time for loading and executing an architecture verification program for a system-on-a-chip (SoC) are provided. The mechanisms of the illustrative embodiments reorganize the scan chains of the SoC and provide an algorithm for organizing and pipelining architectural verification program (AVP) data for scanning into the reorganized scan chains. The scan chains are reorganized so as to align the scan cells for memory array data for each memory array across a plurality of scan chains. The scan chains are further reorganized so that each scan chain has unique AVP data, i.e. no scan chain has more than one memory array's information. The pipelining algorithm bundles data according to the length of the scan chain, the maximum size of the memory array data, and the position of the memory array's scan cells in the scan chains.
摘要翻译：提供了一种用于减少用于加载和执行系统级芯片（SoC）的架构验证程序的测试时间的系统和方法。说明性实施例的机制重新组织SoC的扫描链，并提供用于组织和流水线架构验证程序（AVP）数据的算法，用于扫描重组的扫描链。扫描链被重组，以便对齐用于多个扫描链中的每个存储器阵列的存储器阵列数据的扫描单元。扫描链进一步重组，使得每个扫描链具有唯一的AVP数据，即，没有扫描链具有多于一个的存储器阵列的信息。流水线算法根据扫描链的长度，存储器阵列数据的最大大小以及扫描链中存储器阵列的扫描单元的位置来捆绑数据。

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