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1. 发明申请

US20120119342A1 ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：先进的四边平面非引线封装结构及其制造方法
公开(公告)号：US20120119342A1
公开(公告)日：2012-05-17
申请号：US12944695
申请日：2010-11-11
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
IPC分类号： H01L23/495 , H01L21/58 , H01L21/56
CPC分类号： H01L21/4832 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.
摘要翻译：先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。载体包括管芯焊盘和多个引线。引线的内引线被设计成具有弯曲的侧壁，用于增强内引线和周围模塑料之间的粘附。

2. 发明授权

US08115285B2 Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof 有权
标题翻译：具有保护层以提高表面安装及其制造方法的高级四边形扁平无铅芯片封装
公开(公告)号：US08115285B2
公开(公告)日：2012-02-14
申请号：US12192805
申请日：2008-08-15
申请人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
发明人： Chien-Wen Chen , Yi-Shao Lai , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Pao-Huei Chang Chien , Ping-Cheng Hu , Hsu-Yang Lee
IPC分类号： H01L21/00
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/07802 , H01L2924/12041 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2224/85 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, multiple leads, a chip, a package body, and a protective layer. The die pad includes an upper sloped portion, a lower sloped portion, and a peripheral edge region defining a cavity with a cavity bottom. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body. The protective layer substantially covers the lower sloped portion and the lower surface of at least one lead.
摘要翻译：描述半导体封装和相关方法。在一个实施例中，封装包括管芯焊盘，多个引线，芯片，封装体和保护层。管芯焊盘包括上倾斜部分，下倾斜部分和限定具有空腔底部的空腔的周边边缘区域。每个引线包括上倾斜部分和下倾斜部分。芯片设置在腔体底部并耦合到引线。封装体形成在芯片和引线上，基本上填充空腔，并且基本上覆盖芯片焊盘和引线的上倾斜部分。芯片焊盘和引线的下倾斜部分至少部分地从封装主体的下表面向外延伸。保护层基本上覆盖至少一个引线的下倾斜部分和下表面。

3. 发明授权

US08222726B2 Semiconductor device package having a jumper chip and method of fabricating the same 有权
标题翻译：具有跳线芯片的半导体器件封装及其制造方法
公开(公告)号：US08222726B2
公开(公告)日：2012-07-17
申请号：US12748843
申请日：2010-03-29
申请人： Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Jiunn Chen , Ming-Hsiang Cheng
发明人： Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Jiunn Chen , Ming-Hsiang Cheng
IPC分类号： H01L21/50 , H01L23/48 , H01L21/44
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3121 , H01L23/48 , H01L24/05 , H01L24/17 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0652 , H01L2224/0401 , H01L2224/13099 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48599 , H01L2224/4899 , H01L2224/49175 , H01L2224/838 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/014 , H01L2924/0781 , H01L2924/07811 , H01L2924/10253 , H01L2924/15157 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.
摘要翻译：提供半导体器件封装及其制造方法。半导体器件封装包括衬底，第一芯片，跳线芯片，多个第一接合线和多个第二接合线。衬底具有多个接触焊盘。第一芯片通过第一接合线布置并电连接到基板。跳线芯片设置在第一芯片上并且具有多个金属焊盘。每个金属焊盘分别经由两个第二接合线电连接到衬底的两个接触焊盘。

4. 发明申请

US20090051048A1 Package structure and manufacturing method thereof 审中-公开
标题翻译：包装结构及其制造方法
公开(公告)号：US20090051048A1
公开(公告)日：2009-02-26
申请号：US12222610
申请日：2008-08-13
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/32 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/91 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/81136 , H01L2224/81192 , H01L2224/81801 , H01L2224/83051 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure.
摘要翻译：提供一种封装结构及其制造方法。封装结构包括载体，芯片结合结构和芯片。芯片接合结构形成在载体的第一表面上。芯片结合结构包括空腔，坝，几个通孔和几个焊料凸块。焊料凸块被容纳在通孔中并且对应于位于载体上的第一连接焊盘。芯片嵌入在芯片结合结构的空腔中。芯片的有源表面被牢固地粘贴在芯片接合结构的第一表面上，并且第一焊盘与相应的焊料凸块形成电接触。封装结构的芯片精确地布置在载体上，不仅简化了制造工艺，而且还在封装结构的芯片和载体之间形成稳定的电连接。

5. 发明授权

US08368216B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08368216B2
公开(公告)日：2013-02-05
申请号：US12872644
申请日：2010-08-31
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/538 , H01L21/60 , H01L23/488
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/568 , H01L23/3114 , H01L24/27 , H01L25/0652 , H01L25/50 , H01L2224/1184 , H01L2224/131 , H01L2224/1329 , H01L2224/16145 , H01L2224/2784 , H01L2224/73104 , H01L2224/73204 , H01L2224/81005 , H01L2224/81801 , H01L2224/8185 , H01L2224/831 , H01L2225/06513 , H01L2924/15311 , H01L2924/15321 , H01L2924/014
摘要： The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.
摘要翻译：本发明涉及具有至少一个第一层芯片，多个第一金属凸块，至少一个第二层芯片和封装体的半导体封装。第一层芯片包括设置有第一金属凸块的第一有源表面和与第一有源表面相邻设置的多个第一信号耦合焊盘。第二层芯片电连接到第一层芯片，并且包括面向第一有源表面的第二有源表面和多个第二信号耦合焊盘。第二信号耦合焊盘电容耦合到第一信号耦合焊盘，以便提供第一层芯片和第二层芯片之间的接近通信。封装体封装第一层芯片，第一金属凸块和第二层芯片，并且第一金属凸块部分地露出。

6. 发明申请

US20110278739A1 Semiconductor Package 审中-公开
标题翻译：半导体封装
公开(公告)号：US20110278739A1
公开(公告)日：2011-11-17
申请号：US12777442
申请日：2010-05-11
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Ming-Kun Chen , Hsiao-Chuan Chang , Ming-Hsiang Cheng
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/48 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/1815 , H01L2924/19104 , H01L2924/19105 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.
摘要翻译：本发明涉及半导体封装。半导体封装包括衬底，第一芯片和插入器。第一芯片机械地和电连接到基板。插入器的一些信号焊盘电容耦合到第一芯片的一些信号焊盘，以便在第一芯片和插入器之间提供接近通信。由此，电容耦合的信号焊盘可以以细间距制成，因此半导体封装的尺寸减小，信号焊盘的密度增加。

7. 发明授权

US07980757B2 Bonding strength measuring device 有权
标题翻译：接合强度测量装置
公开(公告)号：US07980757B2
公开(公告)日：2011-07-19
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01K1/00 , G01N25/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译：提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。测量装置包括加热平台，加热滑板和固定支架。加热平台具有第一加热区域和第一可更换夹具。基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。加热滑板具有第二加热区域和第二可更换夹具。第二加热区域用于加热模塑料，第二可更换夹具具有容纳模塑料的空腔。固定支架用于将加热滑板固定在加热平台上。

8. 发明申请

US20090175312A1 BONDING STRENGTH MEASURING DEVICE 有权
标题翻译：粘结强度测量装置
公开(公告)号：US20090175312A1
公开(公告)日：2009-07-09
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01N3/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译：提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。测量装置包括加热平台，加热滑板和固定支架。加热平台具有第一加热区域和第一可更换夹具。基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。加热滑板具有第二加热区域和第二可更换夹具。第二加热区域用于加热模塑料，第二可更换夹具具有用于容纳模塑料的空腔。固定支架用于将加热滑板固定在加热平台上。

9. 发明授权

US08421242B2 Semiconductor package 有权
标题翻译：半导体封装
公开(公告)号：US08421242B2
公开(公告)日：2013-04-16
申请号：US12651087
申请日：2009-12-31
申请人： Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Chang-Lin Yeh , Ming-Hsiang Cheng
发明人： Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Chang-Lin Yeh , Ming-Hsiang Cheng
IPC分类号： H01L23/48
CPC分类号： H01L23/16 , H01L23/13 , H01L23/3121 , H01L23/48 , H01L23/562 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/91 , H01L25/0652 , H01L25/0657 , H01L2224/13099 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73265 , H01L2224/83192 , H01L2224/838 , H01L2225/06517 , H01L2225/06531 , H01L2225/06562 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/12044 , H01L2924/15787 , H01L2924/30107 , H01L2924/00 , H01L2924/3512 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor package is provided. The semiconductor package includes an organic substrate, a stiffness layer, and a chip subassembly. The stiffness layer is formed on the organic substrate. The chip subassembly is disposed on the stiffness layer. The chip subassembly includes at least a first chip, a second chip, and a third chip. The second chip is disposed between the first chip and the third chip in a stacked orientation. The first chip, the second chip, and the third chip have the function of proximity communication.
摘要翻译：提供半导体封装。半导体封装包括有机衬底，刚度层和芯片子组件。刚性层形成在有机基底上。芯片组件设置在刚度层上。芯片子组件至少包括第一芯片，第二芯片和第三芯片。第二芯片以堆叠取向布置在第一芯片和第三芯片之间。第一芯片，第二芯片和第三芯片具有接近通信的功能。

10. 发明授权

US08274149B2 Semiconductor device package having a buffer structure and method of fabricating the same 有权
标题翻译：具有缓冲结构的半导体器件封装及其制造方法
公开(公告)号：US08274149B2
公开(公告)日：2012-09-25
申请号：US12749191
申请日：2010-03-29
申请人： Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ming-Hsiang Cheng
发明人： Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ming-Hsiang Cheng
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L21/563 , H01L23/48 , H01L23/5389 , H01L23/562 , H01L24/73 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2224/131 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/30155 , H01L2224/30181 , H01L2224/73103 , H01L2224/73153 , H01L2224/73203 , H01L2224/73204 , H01L2224/92143 , H01L2224/92242 , H01L2224/97 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/00014 , H01L2924/01014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are disposed on and electrically connected to the first surface and around the cavity. The active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure. The bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips.
摘要翻译：公开了一种半导体器件封装及其制造方法。半导体器件封装包括衬底，缓冲结构，两个有源芯片和桥接芯片。衬底具有空腔，第一表面和与第一表面相对的第二表面。空腔从第一表面延伸到第二表面，并且缓冲结构设置在空腔中。有源芯片设置在第一表面上并且电连接到第一表面并且围绕空腔。活性芯片都具有第一活性表面。桥芯片设置在空腔中并在缓冲结构上方。桥芯片具有第二有源表面，第二有源表面面向第一有源表面并且与第一有源表面部分地重叠，桥芯片用于提供有源芯片之间的邻近通信。

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