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1. 发明授权

US07149955B1 Encoding and decoding apparatus and method with hamming weight enhancement 有权
标题翻译：具有汉明重量增强的编码和解码装置和方法
公开(公告)号：US07149955B1
公开(公告)日：2006-12-12
申请号：US10074747
申请日：2002-02-11
申请人： Pantas Sutardja , Toai Doan
发明人： Pantas Sutardja , Toai Doan
IPC分类号： H03M13/00 , H03M5/00 , H04L1/00
CPC分类号： H03M13/19 , H03M13/31 , H04L1/0041 , H04L1/0054
摘要： A Hamming weight encoder includes an input that receives user data including P symbols and a Hamming weight module that determines a Hamming weight of N of said P symbols. N and P are integers greater than one and N is less than or equal to P. The Hamming weight encoder also includes a comparing module that compares the Hamming weight to a Hamming weight threshold and an inverting module that selectively bitwise inverts bits in said N symbols based on said comparison.
摘要翻译：汉明权重编码器包括接收包括P符号的用户数据的输入和确定所述P个符号的N的汉明权重的汉明权重模块。 N和P是大于1的整数，N小于或等于P. Hamming权重编码器还包括比较模块，其将汉明权重与汉明权重阈值进行比较，反相模块选择性地将所述N个符号中的比特基于所述比较。

2. 发明授权

US08359498B1 Encoding and decoding apparatus and method with hamming weight enhancement 有权
标题翻译：具有汉明重量增强的编码和解码装置和方法
公开(公告)号：US08359498B1
公开(公告)日：2013-01-22
申请号：US11606510
申请日：2006-11-30
申请人： Pantas Sutardja , Toai Doan
发明人： Pantas Sutardja , Toai Doan
IPC分类号： G06F11/00 , H03M13/00 , H04L1/00
CPC分类号： H03M13/19 , H03M13/31 , H04L1/0041 , H04L1/0054
摘要： A method of communicating a bitstream having a characteristic Hamming weight to a destination via a channel comprises determining the characteristic Hamming weight of the bitstream, inverting each bit in the bitstream if the characteristic Hamming weight of the bitstream is below a threshold value and developing an indication of whether the bits in the bitstream are inverted, delivering the bitstream and the indication of whether the bits in the bitstream are inverted to the destination via the channel, and inverting each bit in the bitstream at the destination if the indication indicates that the bits are inverted.
摘要翻译：经由信道将具有特征汉明权重的比特流传送到目的地的方法包括：如果比特流的特征汉明权重低于阈值，则确定比特流的特征汉明权重，反转比特流中的每个比特，并且开发指示比特流中的比特是否被反转，传送比特流以及比特流中的比特是否经由信道被反向到目的地的指示，以及如果指示表明比特是比特，则反转比特流中的每个比特倒。

3. 发明授权

US07535955B1 Methods, algorithms, software, architectures, systems and circuitry for adaptive filtering and/or minimizing a sequence detector error rate 有权
标题翻译：用于自适应滤波和/或使序列检测器误码率最小化的方法，算法，软件，架构，系统和电路
公开(公告)号：US07535955B1
公开(公告)日：2009-05-19
申请号：US10623031
申请日：2003-07-17
申请人： Pantas Sutardja , Toai Doan
发明人： Pantas Sutardja , Toai Doan
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03681
摘要： Methods, algorithms, software, architectures, systems and circuits for targeting certain dominant error types in an adaptive FIR filter and/or signal equalizer. The method and algorithm generally include processing a data sequence in accordance with the adaptive algorithm to produce a processed data sequence, filtering the data sequence to generate a filtered data term for the adaptive algorithm, generating a filtered error term for the adaptive algorithm from at least the processed data sequence, and updating the adaptive algorithm in response to the filtered data and error terms. The architectures generally include an equalizer configured to equalize and/or filter a data sequence and provide an equalized data output, a first filter configured to receive the data sequence and generate a filtered data term for the adaptive algorithm, and an error term circuit configured to receive the equalized data output and provide a filtered error term for the adaptive algorithm.
摘要翻译：用于针对自适应FIR滤波器和/或信号均衡器中的某些主要误差类型的方法，算法，软件，架构，系统和电路。所述方法和算法通常包括根据自适应算法处理数据序列以产生经处理的数据序列，对数据序列进行过滤以产生用于自适应算法的滤波数据项，从至少为自适应算法生成滤波误差项处理的数据序列，以及响应于经滤波的数据和误差项更新自适应算法。该体系结构通常包括均衡器，其被配置为均衡和/或过滤数据序列并提供均衡的数据输出;第一过滤器，被配置为接收数据序列并为自适应算法生成经滤波的数据项;以及错误项电路，被配置为接收均衡的数据输出并为自适应算法提供一个滤波的误差项。

4. 发明授权

US08583991B1 High density multi-level memory 有权
标题翻译：高密度多级存储器
公开(公告)号：US08583991B1
公开(公告)日：2013-11-12
申请号：US13542353
申请日：2012-07-05
申请人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
发明人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
摘要翻译：本发明的实施例提供了高密度，多级存储器。因此，本发明的各种实施例提供了根据本发明的各种实施例的存储器装置，其包括包括多个单元的存储器块，每个单元适于用多电平信号进行操作。这种存储装置还包括适于根据有利地实现多电平信号的多电平分布的编码方案对数据值进行编码的信道块，并且输出编码数据的相应多电平信号值到内存块。可以描述和要求保护其他实施例。

5. 发明授权

US08219886B1 High density multi-level memory 有权
标题翻译：高密度多级存储器
公开(公告)号：US08219886B1
公开(公告)日：2012-07-10
申请号：US11614868
申请日：2006-12-21
申请人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
发明人： Pantas Sutardja , Zining Wu , Toai Doan , Aditya Ramamoorthy
IPC分类号： G06F11/00
CPC分类号： G06F11/1072 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2029/0411
摘要： Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.
摘要翻译：本发明的实施例提供了高密度，多级存储器。因此，本发明的各种实施例提供了根据本发明的各种实施例的存储器装置，其包括包括多个单元的存储器块，每个单元适于用多电平信号进行操作。这种存储装置还包括适于根据有利地实现多电平信号的多电平分布的编码方案对数据值进行编码的信道块，并且输出编码数据的相应多电平信号值到内存块。可以描述和要求保护其他实施例。

6. 发明授权

US07715135B1 Methods, circuits, apparatus, and systems for read channel synchronization and/or fly height measurement 有权
标题翻译：用于读通道同步和/或飞高测量的方法，电路，装置和系统
公开(公告)号：US07715135B1
公开(公告)日：2010-05-11
申请号：US11453219
申请日：2006-06-13
申请人： Pantas Sutardja , Toai Doan , Zining Wu , Michael Madden
发明人： Pantas Sutardja , Toai Doan , Zining Wu , Michael Madden
IPC分类号： G11B20/14
CPC分类号： G11B20/1403 , G11B5/40 , G11B5/6005 , G11B5/6029 , G11B20/1217 , G11B2020/1232 , G11B2020/1287
摘要： Methods, circuits, and systems for processing a preamble field in a read channel (e.g., in a magnetic storage device such as a hard disk drive). The methods generally include the steps of (a) reading the preamble field, wherein the preamble field comprises a repetitive bit pattern having a logical transition every x bit periods, where x is an integer of at least 3 when d is 0 or 1, or where x is an integer of at least d+2 when d is greater than 1, and (b) processing the repetitive bit pattern. The methods may further relate to processing the preamble for synchronization with the read channel and/or for measuring the fly height of a read/write head. The invention also relates to methods of enabling read channel synchronization and/or fly height measurement. The circuitry for fly height measurement generally includes (a) reading logic configured to read a preamble field from a read channel, wherein the preamble field comprises a repetitive bit pattern, (b) determination logic configured to determine a characteristic of the repetitive bit pattern, and (c) correlation logic configured to correlate the characteristic to the fly height. The systems generally comprise those that include a circuit embodying one or more of the inventive concepts disclosed herein. The present invention advantageously provides improved resolution of signals resulting from the preamble fields and of harmonics of said signals, and enables fly height measurement and improved channel synchronization without consuming dedicated tracks, platters, etc. on a magnetic recording medium.
摘要翻译：用于处理读通道（例如，诸如硬盘驱动器的磁存储设备）中的前导码字段的方法，电路和系统。这些方法通常包括以下步骤：（a）读取前导字段，其中前导字段包括每x位周期具有逻辑转换的重复位模式，其中当d为0或1时x为至少3的整数，或其中当d大于1时x是至少d + 2的整数，以及（b）处理重复位模式。该方法还可以涉及处理与读取信道同步的前导码和/或用于测量读/写头的飞行高度。本发明还涉及使能读取通道同步和/或飞行高度测量的方法。用于飞行高度测量的电路通常包括（a）读取逻辑，其被配置为从读取通道读取前导码字段，其中前导码字段包括重复位模式，（b）确定逻辑，其被配置为确定重复位模式的特性，以及（c）相关逻辑，被配置为将特征与飞行高度相关联。系统通常包括包含体现本文公开的一个或多个发明构思的电路的系统。本发明有利地提供了由前导字段和所述信号的谐波产生的信号的改进的分辨率，并且使得能够进行飞行高度测量和改进的信道同步，而不需要在磁记录介质上消耗专用的轨道，拼盘等。

7. 发明授权

US07802151B1 Encoding and decoding apparatus and method with hamming weight enhancement 有权
标题翻译：具有汉明重量增强的编码和解码装置和方法
公开(公告)号：US07802151B1
公开(公告)日：2010-09-21
申请号：US11606677
申请日：2006-11-30
申请人： Pantas Sutardja , Toai Doan
发明人： Pantas Sutardja , Toai Doan
IPC分类号： G06F11/00 , H03M13/00 , H04L1/00
CPC分类号： H03M13/19 , H03M13/31 , H04L1/0041 , H04L1/0054
摘要： A communication decoding method comprises receiving processed binary data including a binary code word and an indication of whether bits of the binary code word are inverted and inverting each bit of the binary code word if the indication indicates that the bits are inverted.
摘要翻译：一种通信解码方法，包括接收处理后的二进制数据，包括二进制码字和二进制码字的位是否反相，如果该指示表明该位被反转则反转二进制码字的每一位。

8. 发明授权

US07783937B1 Encoding and decoding apparatus and method with hamming weight enhancement 有权
标题翻译：具有汉明重量增强的编码和解码装置和方法
公开(公告)号：US07783937B1
公开(公告)日：2010-08-24
申请号：US11606678
申请日：2006-11-30
申请人： Pantas Sutardja , Toai Doan
发明人： Pantas Sutardja , Toai Doan
IPC分类号： G06F11/00 , H03M13/00 , H04L1/00
CPC分类号： H03M13/19 , H03M13/31 , H04L1/0041 , H04L1/0054
摘要： A method comprises obtaining a first sequence of binary digits that collectively have a characteristic Hamming weight, inverting each of the binary digits in the first sequence of binary digits if the Hamming weight of the first sequence of binary digits is below a predetermined threshold Hamming weight value, and providing an indication of whether the binary digits in the first sequence of binary digits have been inverted.
摘要翻译：一种方法包括：如果二进制数字的第一序列的汉明权重低于预定阈值汉明权重值，则获得共同具有特征汉明权重的二进制数字的第一序列，反转第二二进制数位序列中的每个二进制数字并且提供二进制数字的第一序列中的二进制数字是否已被反转的指示。

9. 发明授权

US08441751B1 Dibit pulse extraction methods and systems 有权
标题翻译： Dibit脉冲提取方法和系统
公开(公告)号：US08441751B1
公开(公告)日：2013-05-14
申请号：US11840682
申请日：2007-08-17
申请人： Hongwei Song , Zining Wu , Jingfeng Liu , Toai Doan
发明人： Hongwei Song , Zining Wu , Jingfeng Liu , Toai Doan
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10222 , G11B2220/2516
摘要： A receiving device may be configured to derive an oversampled dibit pulse response estimate using symbols sampled at substantially the read channel symbol rate of the receiving device. The receiving device may include a data acquisition circuit configured to digitize data derived from a memory medium, a symbol timing loop and read circuit, as well as a dibit pulse estimation circuit configured to estimate the oversampled dibit pulse response using symbols sampled at the read channel rate of the receiving device without disturbing the symbol timing loop and read circuit.
摘要翻译：接收设备可以被配置为使用在接收设备的基本读取的信道符号率处采样的符号来导出过采样的双位脉冲响应估计。接收设备可以包括数据获取电路，其被配置为数字化从存储介质导出的数据，符号定时循环和读取电路，以及配置为使用在读取通道上采样的符号来估计过采样双位脉冲响应的双位脉冲估计电路接收设备的速率，而不会干扰符号定时循环和读取电路。

10. 发明授权

US08077419B1 Method and apparatus for adjusting a gain of a variable gain amplifier in a read channel module 有权
标题翻译：用于调整读通道模块中的可变增益放大器的增益的方法和装置
公开(公告)号：US08077419B1
公开(公告)日：2011-12-13
申请号：US12906886
申请日：2010-10-18
申请人： Vasudev V. Pai , Toai Doan , Hongying Sheng
发明人： Vasudev V. Pai , Toai Doan , Hongying Sheng
IPC分类号： G11B5/35
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10037 , G11B20/10055 , G11B20/10222 , G11B20/10314 , G11B20/14 , G11B2220/2516 , G11B2220/2562
摘要： A read-channel module including a VGA module to amplify a signal based on a variable gain, an ADC module to generate a sample based on the amplified signal, and an AGC module to control the variable gain of the VGA module. A gain adjusting module generates (i) a first gain and (ii) a second gain when an amplitude of the sample is (i) less than or equal to a first predetermined threshold and (ii) greater than or equal to a second predetermined threshold, respectively. The AGC module (i) increases and (ii) decreases the variable gain of the VGA module based on (i) the first gain and (ii) the second gain, respectively. The gain adjusting module generates the first gain and the second gain by (i) multiplying a present gain of the AGC module by a predetermined multiplier or (ii) adding a predetermined offset to the present gain.
摘要翻译：一个读通道模块，包括一个基于可变增益放大信号的VGA模块，一个基于放大信号产生采样的ADC模块，以及一个控制VGA模块可变增益的AGC模块。当样本的幅度为（i）小于或等于第一预定阈值时，增益调整模块产生（i）第一增益和（ii）第二增益，以及（ii）大于或等于第二预定阈值，分别。 AGC模块（i）增加并且（ii）分别基于（i）第一增益和（ii）第二增益来降低VGA模块的可变增益。增益调整模块通过（i）将AGC模块的当前增益乘以预定乘数或（ii）将预定偏移量加到当前增益上来产生第一增益和第二增益。

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