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    • 4. 发明授权
    • Synchronous repeatable run out field detection with high efficiency field format
    • 具有高效率场格式的同步可重复运行场外检测
    • US07773328B1
    • 2010-08-10
    • US12009096
    • 2008-01-16
    • Supaket KatchmartHenri SutiosoPantas Sutardja
    • Supaket KatchmartHenri SutiosoPantas Sutardja
    • G11B5/09
    • G11B5/59627
    • A hard disk control system comprises a phase adjust module, an offset adjust module, and a read/write timing module. The phase adjust module generates a phase adjust signal based on a phase difference between a first repeatable run out (RRO) field and a servo wedge field. The offset adjust module outputs a position calibration pattern to a storage medium based on the phase adjust signal; receives at least a portion of the position calibration pattern from the storage medium; and determines an offset based on a comparison between the output position calibration pattern and the received portion of the position calibration pattern. The read/write timing module determines a position to write a second RRO field on the storage medium based on the offset.
    • 硬盘控制系统包括相位调整模块,偏移调整模块和读/写定时模块。 相位调整模块基于第一可重复输出(RRO)场和伺服楔场之间的相位差产生相位调整信号。 偏移调整模块基于相位调整信号将位置校准模式输出到存储介质; 从所述存储介质接收所述位置校准图案的至少一部分; 并且基于输出位置校准图案与位置校准图案的接收部分之间的比较来确定偏移。 读/写定时模块基于偏移来确定在存储介质上写入第二RRO字段的位置。
    • 5. 发明授权
    • Method and apparatus for initial self-servo writing
    • 初始自伺服写入的方法和装置
    • US08879190B1
    • 2014-11-04
    • US13554642
    • 2012-07-20
    • Supaket KatchmartDavid LiawJerome F. RichgelsHenri Sutioso
    • Supaket KatchmartDavid LiawJerome F. RichgelsHenri Sutioso
    • G11B5/02
    • G11B5/59666G11B20/10222
    • Embodiments of the present disclosure provide a method of self-servo writing, the method comprising actions of positionally tracking a selected timing track of a data storage disk, wherein the selected timing track has one or more timing segments; synchronizing an angular position signal to rotation of the data storage disk based on at least one of the one or more timing segments of the selected timing track; specifying servo sector positions relative to the synchronized angular position signal; writing servo sectors to the data storage disk at the specified servo sector positions relative to the synchronized angular position signal; detecting one or more positional errors in timing segments of a next timing track of the data storage disk based at least in part on the synchronized angular position signal; and accounting for the detected one or more positional errors in writing subsequent servo tracks. Other embodiments are also described.
    • 本公开的实施例提供了一种自伺服写入的方法,该方法包括对数据存储盘的选定的定时轨道进行位置跟踪的动作,其中所选择的定时轨道具有一个或多个定时段; 基于所选定时轨道的一个或多个定时段中的至少一个,将角位置信号与数据存储盘的旋转同步; 指定相对于同步角位置信号的伺服扇区位置; 在相对于同步角位置信号的指定伺服扇区位置将伺服扇区写入数据存储盘; 至少部分地基于所述同步角位置信号来检测所述数据存储盘的下一定时轨道的定时段中的一个或多个位置误差; 并且考虑在写入后续伺服磁道时检测到的一个或多个位置误差。 还描述了其它实施例。
    • 10. 发明授权
    • Circuits, architectures, a system and methods for improved clock data recovery
    • 电路,架构,改进时钟数据恢复的系统和方法
    • US07864912B1
    • 2011-01-04
    • US11975495
    • 2007-10-19
    • Lei WuHenri Sutioso
    • Lei WuHenri Sutioso
    • H03D3/24
    • H04L7/033H03L7/07H03L7/0805H03L7/0807H03L7/0814H03L7/093H04L7/0025
    • Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of sampling the data stream at predetermined times, generating clock frequency information and clock phase information from sampled data, and altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of a potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.
    • 电路,架构,时钟数据恢复的系统和方法。 电路通常包括时钟相位调整电路,接收时钟相位信息并提供时钟相位调整信号,时钟频率调整电路,接收时钟频率信息和提供时钟频率调整信号,以及加法电路,接收时钟相位调整 信号和时钟频率调整信号,并提供时钟恢复调整信号。 架构和/或系统通常包括包括体现本文公开的一个或多个本发明构思的时钟数据恢复电路的结构和/或系统。 该方法通常包括以下步骤:在预定时间采样数据流,从采样数据产生时钟频率信息和时钟相位信息,以及响应于时钟频率信息和时钟改变时钟信号的频率和/或相位 相位信息。 本发明防止或减少潜在的非会聚/时钟失控问题的可能性,有利地是对现有设计和逻辑的最小化或不变化。 本发明进一步有利地利用最小的附加电路提高了系统稳定性,可靠性和性能。