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    • 3. 发明授权
    • Circuits, architectures, a system and methods for improved clock data recovery
    • 电路,架构,改进时钟数据恢复的系统和方法
    • US07864912B1
    • 2011-01-04
    • US11975495
    • 2007-10-19
    • Lei WuHenri Sutioso
    • Lei WuHenri Sutioso
    • H03D3/24
    • H04L7/033H03L7/07H03L7/0805H03L7/0807H03L7/0814H03L7/093H04L7/0025
    • Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of sampling the data stream at predetermined times, generating clock frequency information and clock phase information from sampled data, and altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of a potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.
    • 电路,架构,时钟数据恢复的系统和方法。 电路通常包括时钟相位调整电路,接收时钟相位信息并提供时钟相位调整信号,时钟频率调整电路,接收时钟频率信息和提供时钟频率调整信号,以及加法电路,接收时钟相位调整 信号和时钟频率调整信号,并提供时钟恢复调整信号。 架构和/或系统通常包括包括体现本文公开的一个或多个本发明构思的时钟数据恢复电路的结构和/或系统。 该方法通常包括以下步骤:在预定时间采样数据流,从采样数据产生时钟频率信息和时钟相位信息,以及响应于时钟频率信息和时钟改变时钟信号的频率和/或相位 相位信息。 本发明防止或减少潜在的非会聚/时钟失控问题的可能性,有利地是对现有设计和逻辑的最小化或不变化。 本发明进一步有利地利用最小的附加电路提高了系统稳定性,可靠性和性能。
    • 4. 发明授权
    • Apparatus for clock data recovery
    • 时钟数据恢复装置
    • US07295644B1
    • 2007-11-13
    • US10619278
    • 2003-07-14
    • Lei WuHenri Sutioso
    • Lei WuHenri Sutioso
    • H03D3/24
    • H03L7/0807H03L7/0891H03L7/093
    • Circuits, architectures, a system and methods for clock data recovery. The circuit generally includes (a) a clock phase adjustment circuit, receiving clock phase information and providing a clock phase adjustment signal, (b) a clock frequency adjustment circuit, receiving clock frequency information and providing a clock frequency adjustment signal, and (c) an adder circuit, receiving the clock phase adjustment signal and the clock frequency adjustment signal, and providing a clock recovery adjustment signal. The architectures and/or systems generally comprise those that include a clock data recovery circuit embodying one or more of the inventive concepts disclosed herein. The method generally comprises the steps of (1) sampling the data stream at predetermined times, (2) generating clock frequency information and clock phase information from sampled data, and (3) altering a frequency and/or a phase of the clock signal in response to the clock frequency information and the clock phase information. The present invention prevents or reduces the likelihood of the potential nonconvergence/clock runaway problem, advantageously with minimal or no changes to existing designs and logic. The present invention further advantageously improves system stability, reliability and performance with a minimum of additional circuitry.
    • 电路,架构,时钟数据恢复的系统和方法。 电路通常包括(a)时钟相位调整电路,接收时钟相位信息并提供时钟相位调整信号,(b)时钟频率调整电路,接收时钟频率信息和提供时钟频率调整信号,以及(c) 加法电路,接收时钟相位调整信号和时钟频率调整信号,并提供时钟恢复调整信号。 架构和/或系统通常包括包括体现本文公开的一个或多个本发明构思的时钟数据恢复电路的结构和/或系统。 该方法通常包括以下步骤:(1)在预定时间对数据流进行采样,(2)从采样数据生成时钟频率信息和时钟相位信息,以及(3)改变时钟信号的频率和/ 响应于时钟频率信息和时钟相位信息。 本发明防止或减少潜在的非会聚/时钟失控问题的可能性,有利地是对现有设计和逻辑的最小化或不变化。 本发明进一步有利地利用最小的附加电路提高了系统稳定性,可靠性和性能。
    • 5. 发明授权
    • Clock offset compensator
    • 时钟偏移补偿器
    • US07263153B2
    • 2007-08-28
    • US10267177
    • 2002-10-09
    • Henri SutiosoLei Wu
    • Henri SutiosoLei Wu
    • H03D3/24
    • G06F1/10H03L7/081H03L7/197H04L7/0337
    • A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a signal having a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.
    • 设备与主机通信,并且包括发射机,接收机和时钟发生器,其产生具有本地时钟频率的信号。 时钟恢复电路与接收机通信,并从接收机从主机接收的数据恢复主机时钟频率。 频率偏移电路与时钟恢复电路和时钟发生器通信,并且基于时钟频率和恢复的主机时钟频率产生频率偏移。 频率补偿器使用频率偏移补偿发射机的频率。 主机和设备可以使用串行ATA标准进行通信。 可以在扩频操作期间进行频率补偿。
    • 7. 发明授权
    • Visual language modeling for image classification
    • 图像分类的视觉语言建模
    • US08126274B2
    • 2012-02-28
    • US11847959
    • 2007-08-30
    • Mingjing LiWei-Ying MaZhiwei LiLei Wu
    • Mingjing LiWei-Ying MaZhiwei LiLei Wu
    • G06K9/62
    • G06K9/4685G06K9/4642G06K9/6278
    • Systems and methods for visual language modeling for image classification are described. In one aspect the systems and methods model training images corresponding to multiple image categories as matrices of visual words. Visual language models are generated from the matrices. In view of a given image, for example, provided by a user or from the Web, the systems and methods determine an image category corresponding to the given image. This image categorization is accomplished by maximizing the posterior probability of visual words associated with the given image over the visual language models. The image category, or a result corresponding to the image category, is presented to the user.
    • 描述了用于图像分类的视觉语言建模的系统和方法。 在一个方面,系统和方法将对应于多个图像类别的训练图像建模为视觉词的矩阵。 视觉语言模型是从矩阵生成的。 考虑到例如由用户或从Web提供的给定图像,系统和方法确定对应于给定图像的图像类别。 这种图像分类是通过在视觉语言模型上最大化与给定图像相关联的视觉词的后验概率来实现的。 图像类别或与图像类别对应的结果被呈现给用户。
    • 8. 发明授权
    • Architectures, circuits, systems and methods for reducing latency in data communications
    • 用于减少数据通信延迟的架构,电路,系统和方法
    • US07835425B1
    • 2010-11-16
    • US12330218
    • 2008-12-08
    • Pantas SutardjaLei WuHongying Sheng
    • Pantas SutardjaLei WuHongying Sheng
    • H03K11/00H04L25/60H04L25/64
    • G06F13/405
    • Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal. The systems generally relate to those that include the present architecture and/or circuit. The method generally includes determining a phase difference between first and second periodic signals, one of the periodic signals being recovered from a data stream; adjusting the other periodic signal in response to the phase difference and filtered information from the recovered periodic signal; and transmitting the data stream in accordance with said adjusted periodic signal. The present invention advantageously eliminates a FIFO memory in the data path, thereby reducing transceiver latency and improving system performance.
    • 用于促进数据通信和/或减少数据通信中的延迟的电路,架构,系统和方法。 该架构包括时钟恢复环路,其接收来自主机设备的数据并提供恢复的时钟信号,滤波器电路接收恢复的时钟信号信息,并提供响应于恢复的时钟信号信息和两个时钟信号调整发射机时钟的控制信号 以及接收控制信号并根据发射机时钟向目的地设备发送数据的发射机。 电路通常包括时钟对准块,其接收第一和第二周期信号并响应于此提供控制信号,用于第一周期性信号信息的滤波器以及被配置为组合控制信号和滤波信息的逻辑电路,由此提供调整 信号用于第二周期信号。 系统通常涉及包括本架构和/或电路的系统。 该方法通常包括确定第一和第二周期信号之间的相位差,从数据流中恢复一个周期信号; 响应于来自恢复的周期信号的相位差和滤波信息调整另一周期信号; 以及根据所述调整的周期信号发送数据流。 本发明有利地消除数据路径中的FIFO存储器,从而减少收发机等待时间并提高系统性能。