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1. 发明申请

US20060206646A1 Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set 审中-公开
标题翻译：具有具有可编程优先级的中断结构的微控制器，每个优先级与不同的寄存器组相关联
公开(公告)号：US20060206646A1
公开(公告)日：2006-09-14
申请号：US10566515
申请日：2004-07-29
申请人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig Mackenna
发明人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig Mackenna
IPC分类号： G06F13/24 , G06F13/36
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.
摘要翻译：通常，对于处理系统，必须保证在第一个程序流的执行恢复之前所有中断的程序流参数都被恢复。如果在此传输期间发生中断，则所有数据可能不被存储或恢复。如果不发生程序寄存器内容和其他关键的第一程序流数据的无错误存储，则处理器（180）无法知道还原到寄存器的第一程序流数据是否已经被破坏。因此，提供了一种新颖的寄存器架构（120,121,122,123,124,125），其便于中断程序流的处理，而不存储和恢复中断的程序流关键数据。

2. 发明授权

US08392641B2 Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set 有权
标题翻译：具有具有可编程优先级的中断结构的微控制器，每个优先级与不同的寄存器组相关联
公开(公告)号：US08392641B2
公开(公告)日：2013-03-05
申请号：US12785943
申请日：2010-05-24
申请人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig MacKenna
发明人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig MacKenna
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
摘要翻译：本公开的方面涉及具有特别配置的微控制器的系统。在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。

3. 发明申请

US20100299471A1 Microcontroller with an Interrupt Structure Having Programmable Priority Levels with each Priority Level Associated with a Different Register Set 有权
标题翻译：具有中断结构的微控制器，具有与不同寄存器集相关联的每个优先级的可编程优先级
公开(公告)号：US20100299471A1
公开(公告)日：2010-11-25
申请号：US12785943
申请日：2010-05-24
申请人： Pankaj Shrivastava , Gregory Goodhue , Ata khan , Zhimin Ding , Craig Mackenna
发明人： Pankaj Shrivastava , Gregory Goodhue , Ata khan , Zhimin Ding , Craig Mackenna
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
摘要翻译：本公开的方面涉及具有特别配置的微控制器的系统。在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。

4. 发明授权

US07945718B2 Microcontroller waveform generation 失效
标题翻译：微控制器波形生成
公开(公告)号：US07945718B2
公开(公告)日：2011-05-17
申请号：US12064375
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00 , G06F19/00 , G06F1/02
CPC分类号： G06F1/0321 , G06F15/7842
摘要： One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
摘要翻译：本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列的指令来执行不同的过程。

5. 发明授权

US08176281B2 Controlling access to an embedded memory of a microcontroller 有权
标题翻译：控制对微控制器嵌入式存储器的访问
公开(公告)号：US08176281B2
公开(公告)日：2012-05-08
申请号：US12064381
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F12/00
CPC分类号： G01R31/31719 , G01R31/318533 , G06F21/74 , G11C29/48 , G11C2029/0401 , G11C2029/5602
摘要： A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.
摘要翻译：微控制器（30）包括处理器（32），可操作地耦合到处理器（32）的嵌入式存储器（46）和可操作地连接到处理器（32）和存储器（36）的微控制器测试接口（34）。微控制器（30）响应复位信号以执行复位启动，其使得测试接口（34）的初始禁用状态被设置并且与处理器（32）一起执行启动代码。该代码执行可选地建立进一步的禁用状态。微控制器（30）在复位开始之后的微控制器（30）操作期间提供用于存储器（46）访问测试交错（34）的测试接口的使能状态，除非进一步禁用的存储器（46）访问状态由启动代码的执行。

6. 发明申请

US20090254691A1 MICROCONTROLLER WAVEFORM GENERATION 失效
标题翻译：微波炉波形发生器
公开(公告)号：US20090254691A1
公开(公告)日：2009-10-08
申请号：US12064375
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F13/14 , G06F1/02
CPC分类号： G06F1/0321 , G06F15/7842
摘要： One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
摘要翻译：本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列的指令来执行不同的过程。

7. 发明申请

US20090222652A1 EMBEDDED MEMORY PROTECTION 有权
标题翻译：嵌入式存储器保护
公开(公告)号：US20090222652A1
公开(公告)日：2009-09-03
申请号：US12064377
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
IPC分类号： G06F12/14 , G06F11/27 , G06F9/00
CPC分类号： G06F12/1433
摘要： One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
摘要翻译：本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。存储器（46）可通过测试接口（34）访问。响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码以在随后的微控制器（30）操作期间提供禁用状态。

8. 发明申请

US20090204779A1 CONTROLLING EMBEDDED MEMORY ACCESS 有权
标题翻译：控制嵌入式存储器访问
公开(公告)号：US20090204779A1
公开(公告)日：2009-08-13
申请号：US12064381
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F12/08 , G06F12/02 , G06F9/00
CPC分类号： G01R31/31719 , G01R31/318533 , G06F21/74 , G11C29/48 , G11C2029/0401 , G11C2029/5602
摘要： A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.
摘要翻译：微控制器（30）包括处理器（32），可操作地耦合到处理器（32）的嵌入式存储器（46）和可操作地连接到处理器（32）和存储器（36）的微控制器测试接口（34）。微控制器（30）响应复位信号以执行复位启动，其使得测试接口（34）的初始禁用状态被设置并且与处理器（32）一起执行启动代码。该代码执行可选地建立进一步的禁用状态。微控制器（30）在复位开始之后的微控制器（30）操作期间提供用于存储器（46）访问测试交错（34）的测试接口的使能状态，除非进一步禁用的存储器（46）访问状态由启动代码的执行。

9. 发明授权

US08065512B2 Embedded memory protection 有权
标题翻译：嵌入式内存保护
公开(公告)号：US08065512B2
公开(公告)日：2011-11-22
申请号：US12064377
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
IPC分类号： G06F9/00 , G06F17/50 , G06F9/445 , G06F12/00 , G06F9/44 , G06F7/04 , G06F11/00 , G01R27/28
CPC分类号： G06F12/1433
摘要： One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
摘要翻译：本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。存储器（46）可通过测试接口（34）访问。响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码以在随后的微控制器（30）操作期间提供禁用状态。

10. 发明授权

US07446270B2 Interlock assemblies for circuit breakers 有权
标题翻译：断路器联锁组件
公开(公告)号：US07446270B2
公开(公告)日：2008-11-04
申请号：US11646673
申请日：2006-12-28
申请人： Veeresh Somalingayya , Pankaj Shrivastava , Rajanikanta Pradhan
发明人： Veeresh Somalingayya , Pankaj Shrivastava , Rajanikanta Pradhan
IPC分类号： H01H9/20
CPC分类号： H01H9/26 , H01H9/281 , H01H9/286 , H01H2300/018
摘要： An interlock assembly comprising: an interlock plate comprising at least one slot disposed about a central portion thereof, a first locking tab disposed perpendicular to a first side of the interlock plate, and a second locking tab disposed perpendicular to a second side of the interlock plate; and a base disposed adjacent to a bottom surface of the interlock plate, the base comprising at least one perturbation disposed on a surface of the base opposite to the bottom surface of the interlock plate, such that the perturbation is disposed within the slot of the interlock plate, thereby providing the interlock plate with reciprocating movement in relation to the base.
摘要翻译：一种互锁组件，包括：互锁板，包括围绕其中心部分设置的至少一个狭槽，垂直于所述互锁板的第一侧设置的第一锁定突出部和垂直于所述互锁板的第二侧设置的第二锁定突出部 ; 以及邻近所述互锁板的底表面设置的底座，所述底座包括设置在所述底座的与所述互锁板的底表面相对的表面上的至少一个扰动，使得所述扰动设置在所述互锁的所述槽内从而提供互锁板相对于底座的往复运动。

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