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1. 发明授权

US07945718B2 Microcontroller waveform generation 失效
标题翻译：微控制器波形生成
公开(公告)号：US07945718B2
公开(公告)日：2011-05-17
申请号：US12064375
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00 , G06F19/00 , G06F1/02
CPC分类号： G06F1/0321 , G06F15/7842
摘要： One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
摘要翻译：本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列的指令来执行不同的过程。

2. 发明申请

US20060206691A1 Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations 失效
标题翻译：存储器组织允许单周期指针寻址，其中指针的地址也包含在其中一个存储单元中
公开(公告)号：US20060206691A1
公开(公告)日：2006-09-14
申请号：US10566514
申请日：2004-07-27
申请人： Gregory Goodhue , Ata Khan , Zhimin Ding
发明人： Gregory Goodhue , Ata Khan , Zhimin Ding
IPC分类号： G06F9/40
CPC分类号： G06F9/321 , G06F9/3012 , G06F9/3013 , G06F9/3016 , G06F9/35
摘要： All Pointer-based accesses require first that the value contained in a pointer register (200a, 200b, 200c, 200d) to be read and then that value be used as an address to the appropriate region in random access memory (RAM) (104). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory (103a, 103b, 103c, 103d) to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers (200a, 200b, 200c, 200d), a read access involves mutliplexing out of appropriate data for the pointer address from these pointer registers (200a, 200b, 200c, 200d) to form a target pointer address. This target pointer address is then used as an address to access RAM (104) without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM (104).
摘要翻译：所有基于指针的访问首先需要读取指针寄存器（200a，200b，200c，200d）中包含的值，然后将该值用作随机存取存储器（RAM）中适当区域的地址（104）。如今所实现的，这需要两个存储器读取访问周期，每个存储器访问周期至少需要一个时钟周期，因此该实现不允许单周期操作。根据本发明的实施例，当对指针存储器（103a，103b，103c，103d）执行访问以读取指针的内容时，实际上是读取的影子存储器，并且返回指针值。由于阴影存储器由指针寄存器（200a，200b，200c，200d）组成，所以读取访问涉及从这些指针寄存器（200a，200b，200c）中针对指针地址的适当数据进行多路复用，200 d）以形成目标指针地址。然后，该目标指针地址用作访问RAM（104）的地址，而不需要时钟的开销，因为寄存器访问是纯组合的，并且不需要与访问RAM（104）一样的时钟相位相关定时。

3. 发明申请

US20060206646A1 Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set 审中-公开
标题翻译：具有具有可编程优先级的中断结构的微控制器，每个优先级与不同的寄存器组相关联
公开(公告)号：US20060206646A1
公开(公告)日：2006-09-14
申请号：US10566515
申请日：2004-07-29
申请人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig Mackenna
发明人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig Mackenna
IPC分类号： G06F13/24 , G06F13/36
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.
摘要翻译：通常，对于处理系统，必须保证在第一个程序流的执行恢复之前所有中断的程序流参数都被恢复。如果在此传输期间发生中断，则所有数据可能不被存储或恢复。如果不发生程序寄存器内容和其他关键的第一程序流数据的无错误存储，则处理器（180）无法知道还原到寄存器的第一程序流数据是否已经被破坏。因此，提供了一种新颖的寄存器架构（120,121,122,123,124,125），其便于中断程序流的处理，而不存储和恢复中断的程序流关键数据。

4. 发明申请

US20090254691A1 MICROCONTROLLER WAVEFORM GENERATION 失效
标题翻译：微波炉波形发生器
公开(公告)号：US20090254691A1
公开(公告)日：2009-10-08
申请号：US12064375
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F13/14 , G06F1/02
CPC分类号： G06F1/0321 , G06F15/7842
摘要： One embodiment of the present invention is a microcontroller (24) including an embedded memory (42), waveform control circuitry (44) operatively coupled to the memory (42), several terminals (52), and a programmable processor (30). Processor (30) is responsive to execution of the first sequence of instructions to store a waveform bit pattern in memory (42) with a desired transmission timing. Waveform circuitry (44) is responsive to processor (30) to control transmission of the waveform bit pattern stored in memory (42) through one or more of the terminals (52) in accordance with the timing while processor (30) executes the second sequence of instructions to perform a different process.
摘要翻译：本发明的一个实施例是包括嵌入式存储器（42），可操作地耦合到存储器（42）的波形控制电路（44），多个终端（52）和可编程处理器（30））的微控制器（24）。处理器（30）响应于第一指令序列的执行，以将期望的发送定时将波形位模式存储在存储器（42）中。波形电路（44）响应于处理器（30）根据定时控制通过一个或多个终端（52）存储在存储器（42）中的波形位模式的传输，而处理器（30）执行第二序列的指令来执行不同的过程。

5. 发明申请

US20090222652A1 EMBEDDED MEMORY PROTECTION 有权
标题翻译：嵌入式存储器保护
公开(公告)号：US20090222652A1
公开(公告)日：2009-09-03
申请号：US12064377
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithm Nagaraj
IPC分类号： G06F12/14 , G06F11/27 , G06F9/00
CPC分类号： G06F12/1433
摘要： One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
摘要翻译：本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。存储器（46）可通过测试接口（34）访问。响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码以在随后的微控制器（30）操作期间提供禁用状态。

6. 发明申请

US20050021928A1 Memory accelerator for arm processors 有权
标题翻译：手臂处理器的内存加速器
公开(公告)号：US20050021928A1
公开(公告)日：2005-01-27
申请号：US10923284
申请日：2004-08-20
申请人： Gregory Goodhue , Ata Khan , John Wharton , Robert Kallal
发明人： Gregory Goodhue , Ata Khan , John Wharton , Robert Kallal
IPC分类号： G06F12/08 , G06F9/32 , G06F9/38 , G06F12/02 , G06F9/30
CPC分类号： G06F9/3814 , G06F9/3802 , G06F9/381
摘要： A memory accelerator module buffers program instructions and/or data for high speed access using a deterministic access protocol. The program memory is logically partitioned into ‘stripes’, or ‘cyclically sequential’ partitions, and the memory accelerator module includes a latch that is associated with each partition. When a particular partition is accessed, it is loaded into its corresponding latch, and the instructions in the next sequential partition are automatically pre-fetched into their corresponding latch. In this manner, the performance of a sequential-access process will have a known response, because the pre-fetched instructions from the next partition will be in the latch when the program sequences to these instructions. Previously accessed blocks remain in their corresponding latches until the pre-fetch process ‘cycles around’ and overwrites the contents of each sequentially-accessed latch. In this manner, the performance of a loop process, with regard to memory access, will be determined based solely on the size of the loop. If the loop is below a given size, it will be executable without overwriting existing latches, and therefore will not incur memory access delays as it repeatedly executes instructions contained within the latches. If the loop is above a given size, it will overwrite existing latches containing portions of the loop, and therefore require subsequent re-loadings of the latch with each loop. Because the pre-fetch is automatic, and determined solely on the currently accessed instruction, the complexity and overhead associated with this memory acceleration is minimal.
摘要翻译：存储器加速器模块使用确定性访问协议来缓冲用于高速访问的程序指令和/或数据。程序存储器在逻辑上被划分为“条带”或“循环顺序”分区，并且存储器加速器模块包括与每个分区相关联的锁存器。当访问特定分区时，它被加载到其对应的锁存器中，并且下一个顺序分区中的指令被自动预取到其对应的锁存器中。以这种方式，顺序访问过程的性能将具有已知的响应，因为当程序对这些指令进行排序时，来自下一分区的预取指令将在锁存器中。先前访问的块保留在其对应的锁存器中，直到预取处理“周转”并覆盖每个顺序访问的锁存器的内容。以这种方式，关于存储器访问的循环处理的执行将仅基于循环的大小来确定。如果循环低于一个给定的大小，它将可执行而不会覆盖现有的锁存器，因此它不会因为重复执行包含在锁存器内的指令而引起存储器访问延迟。如果循环高于给定尺寸，它将覆盖包含循环部分的现有锁存器，因此需要随后每个循环重新加载锁存器。因为预取是自动的，并且仅根据当前访问的指令确定，与该存储器加速相关联的复杂性和开销是最小的。

7. 发明授权

US08386885B1 Using ECC memory to store configuration information 有权
标题翻译：使用ECC内存来存储配置信息
公开(公告)号：US08386885B1
公开(公告)日：2013-02-26
申请号：US12869649
申请日：2010-08-26
申请人： Ata Khan
发明人： Ata Khan
IPC分类号： G11C29/00
CPC分类号： G11C7/20 , G06F11/1048
摘要： A programmable processing device having a non-volatile memory that may comprise a first memory portion and a second memory portion, where the first section of the first memory portion is configured to store program instructions or data and the second memory portion of the memory word is configured to store either the configuration data or the error detection bits depending upon if an error detection scheme is implemented for the program instructions or data.
摘要翻译：一种具有可包括第一存储器部分和第二存储器部分的非易失性存储器的可编程处理装置，其中第一存储器部分的第一部分被配置为存储程序指令或数据，并且存储器字的第二存储器部分是被配置为存储配置数据或错误检测位，这取决于是否对程序指令或数据执行错误检测方案。

8. 发明授权

US08176281B2 Controlling access to an embedded memory of a microcontroller 有权
标题翻译：控制对微控制器嵌入式存储器的访问
公开(公告)号：US08176281B2
公开(公告)日：2012-05-08
申请号：US12064381
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava
IPC分类号： G06F12/00
CPC分类号： G01R31/31719 , G01R31/318533 , G06F21/74 , G11C29/48 , G11C2029/0401 , G11C2029/5602
摘要： A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.
摘要翻译：微控制器（30）包括处理器（32），可操作地耦合到处理器（32）的嵌入式存储器（46）和可操作地连接到处理器（32）和存储器（36）的微控制器测试接口（34）。微控制器（30）响应复位信号以执行复位启动，其使得测试接口（34）的初始禁用状态被设置并且与处理器（32）一起执行启动代码。该代码执行可选地建立进一步的禁用状态。微控制器（30）在复位开始之后的微控制器（30）操作期间提供用于存储器（46）访问测试交错（34）的测试接口的使能状态，除非进一步禁用的存储器（46）访问状态由启动代码的执行。

9. 发明授权

US08392641B2 Microcontroller with an interrupt structure having programmable priority levels with each priority level associated with a different register set 有权
标题翻译：具有具有可编程优先级的中断结构的微控制器，每个优先级与不同的寄存器组相关联
公开(公告)号：US08392641B2
公开(公告)日：2013-03-05
申请号：US12785943
申请日：2010-05-24
申请人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig MacKenna
发明人： Pankaj Shrivastava , Gregory Goodhue , Ata Khan , Zhimin Ding , Craig MacKenna
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/462 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.
摘要翻译：本公开的方面涉及具有特别配置的微控制器的系统。在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。

10. 发明授权

US08065512B2 Embedded memory protection 有权
标题翻译：嵌入式内存保护
公开(公告)号：US08065512B2
公开(公告)日：2011-11-22
申请号：US12064377
申请日：2006-08-22
申请人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
发明人： Ata Khan , Greg Goodhue , Pankaj Shrivastava , Bas Van Der Veer , Rick Varney , Prithvi Nagaraj
IPC分类号： G06F9/00 , G06F17/50 , G06F9/445 , G06F12/00 , G06F9/44 , G06F7/04 , G06F11/00 , G01R27/28
CPC分类号： G06F12/1433
摘要： One embodiment of the present application includes a microcontroller (30) that has an embedded memory (46), a programmable processor (32), and a test interface (34). The memory (46) is accessible through the test interface (34). In response to resetting this microcontroller (30), a counter is started and the test interface (34) is initially set to a disabled state while an initiation program is executed. The test interface (34) is changed to an enabled state—such that access to the embedded memory (46) is permitted through it—when the counter reaches a predefined value unless the microcontroller (30) executes programming code before the predefined value is reached to provide the disabled state during subsequent microcontroller (30) operation.
摘要翻译：本申请的一个实施例包括具有嵌入式存储器（46），可编程处理器（32）和测试接口（34）的微控制器（30）。存储器（46）可通过测试接口（34）访问。响应于复位该微控制器（30），启动计数器，并且在执行启动程序的同时将测试接口（34）初始设置为禁用状态。测试接口（34）被改变为使能状态，使得通过该接口允许对嵌入式存储器（46）的访问 - 当计数器达到预定值时，除非微控制器（30）在达到预定义值之前执行编程代码以在随后的微控制器（30）操作期间提供禁用状态。

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