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1. 发明授权

US06946716B2 Electroplated interconnection structures on integrated circuit chips 有权
标题翻译：集成电路芯片上的电镀互连结构
公开(公告)号：US06946716B2
公开(公告)日：2005-09-20
申请号：US10773434
申请日：2004-02-09
申请人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： H01L21/288 , H01L21/768 , H01L29/00
CPC分类号： C25D3/38 , C25D5/022 , H01L21/2885 , H01L21/76877 , H01L21/76885
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超量填充特征的能力是独一无二的，优于其他沉积方法。以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

2. 发明授权

US06251528B1 Method to plate C4 to copper stud 失效
标题翻译： C4到铜柱的方法
公开(公告)号：US06251528B1
公开(公告)日：2001-06-26
申请号：US09004808
申请日：1998-01-09
申请人： Cyprian Emeka Uzoh , Daniel C. Edelstein
发明人： Cyprian Emeka Uzoh , Daniel C. Edelstein
IPC分类号： B32B1706
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03602 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/1148 , H01L2224/13006 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/3025 , Y10T428/12299 , Y10T428/12361 , H01L2924/00014 , H01L2224/05552
摘要： A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess.
摘要翻译：一种在不使用掩模的情况下将第二金属直接镀在第一金属上的方法。提供了包括至少一个金属特征和覆盖金属特征和基底的至少一个绝缘层的半导体基板。在至少一个绝缘层中形成至少一个凹槽，从而暴露出金属特征的至少一部分。在绝缘层和金属特征的暴露部分之上形成至少一个导电阻挡层。在至少一个阻挡层上形成第一金属的电镀种子层。在电镀种子层上沉积光致抗蚀剂层。除去至少一个凹部外的光致抗蚀剂层和电镀种子层的部分。残留在至少一个凹部中的光致抗蚀剂被去除。将第二金属电镀到凹槽中的电镀种子层上。

3. 发明授权

US06465376B2 Method and structure for improving electromigration of chip interconnects 失效
标题翻译：改善芯片互连电迁移的方法和结构
公开(公告)号：US06465376B2
公开(公告)日：2002-10-15
申请号：US09377337
申请日：1999-08-18
申请人： Cyprian Emeka Uzoh , Daniel C. Edelstein , Andrew Simon
发明人： Cyprian Emeka Uzoh , Daniel C. Edelstein , Andrew Simon
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76883 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10S977/891 , H01L2924/00
摘要： A microstructure comprises a conductive layer of aluminum, copper or alloys thereof on a substrate wherein the layer comprises metal grains at least about 0.1 microns and barrier material deposited in the grainboundaries of the surface of the metal is provided along with a method for its fabrication.
摘要翻译：微结构包括在基底上的铝，铜或其合金的导电层，其中该层包含至少约0.1微米的金属颗粒，以及沉积在金属表面的晶界中的阻挡材料及其制造方法。

4. 发明授权

US06297140B1 Method to plate C4 to copper stud 有权
标题翻译： C4到铜柱的方法
公开(公告)号：US06297140B1
公开(公告)日：2001-10-02
申请号：US09389232
申请日：1999-09-03
申请人： Cyprian Emeka Uzoh , Daniel C. Edelstein
发明人： Cyprian Emeka Uzoh , Daniel C. Edelstein
IPC分类号： H01L2144
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03602 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05572 , H01L2224/1148 , H01L2224/13006 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04953 , H01L2924/3025 , Y10T428/12299 , Y10T428/12361 , H01L2924/00014 , H01L2224/05552
摘要： A method for plating a second metal directly to a first metal without utilizing a mask. A semiconductor substrate is provided including at least one metal feature and at least one insulating layer covering the metal feature and the substrate. At least one recess is formed in the at least one insulating layer thereby exposing at least a portion of the metal feature. At least one conductive barrier layer is formed over the insulating layer and the exposed portion of the metal feature. A plating seed layer of a first metal is formed over the at least one barrier layer. A photoresist layer is deposited over the plating seed layer. Portions of the photoresist layer and portions of the plating seed layer outside of the at least one recess are removed. Photoresist remaining in the at least one recess is removed. A second metal is electroplated to the plating seed layer in the recess, using the barrier layer to conduct electrical current.
摘要翻译：一种在不使用掩模的情况下将第二金属直接镀在第一金属上的方法。提供了包括至少一个金属特征和覆盖金属特征和基底的至少一个绝缘层的半导体基板。在至少一个绝缘层中形成至少一个凹槽，从而暴露出金属特征的至少一部分。在绝缘层和金属特征的暴露部分之上形成至少一个导电阻挡层。在至少一个阻挡层上形成第一金属的电镀种子层。在电镀种子层上沉积光致抗蚀剂层。除去光致抗蚀剂层的一部分和至少一个凹部外部的电镀种子层的部分。残留在至少一个凹部中的光致抗蚀剂被去除。第二金属被电镀到凹槽中的电镀种子层，使用阻挡层传导电流。

5. 发明申请

US20110003473A1 STRUCTURE FOR METAL CAP APPLICATIONS 有权
标题翻译：金属盖应用结构
公开(公告)号：US20110003473A1
公开(公告)日：2011-01-06
申请号：US12881806
申请日：2010-09-14
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76849
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

6. 发明申请

US20090148677A1 HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 失效
标题翻译：高比例电镀金属特征及方法
公开(公告)号：US20090148677A1
公开(公告)日：2009-06-11
申请号：US11953359
申请日：2007-12-10
申请人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： C25D5/02 , B32B3/00
CPC分类号： C25D5/02 , Y10T428/24331 , Y10T428/24917
摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.
摘要翻译：公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料没有接缝和/或空隙。此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

7. 发明申请

US20130328167A1 SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR 审中-公开
标题翻译：自对准金属绝缘子 - 金属（MIM）电容器
公开(公告)号：US20130328167A1
公开(公告)日：2013-12-12
申请号：US13489940
申请日：2012-06-06
申请人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/75 , H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.
摘要翻译：提供集成在后端（BEOL）结构中的金属 - 绝缘体 - 金属（MIM）电容器结构。 MIM电容器结构包括嵌入在BEOL结构的电介质材料中的下电极，即第一导电材料，具有等于或大于位于下电极顶部的二氧化硅的介电常数的介电材料衬垫，以及位于电介质材料衬垫的垂直部分之间并且位于介电材料衬里的水平连接部分顶部的上电极，即第二导电材料。根据本公开，电介质材料衬垫的垂直部分不延伸到包括下电极的电介质材料的上表面上。

8. 发明授权

US08133810B2 Structure for metal cap applications 有权
标题翻译：金属盖应用结构
公开(公告)号：US08133810B2
公开(公告)日：2012-03-13
申请号：US12881806
申请日：2010-09-14
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L21/44
CPC分类号： H01L21/76885 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76849
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

9. 发明申请

US20100143649A1 HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD 有权
标题翻译：高比例电镀金属特征及方法
公开(公告)号：US20100143649A1
公开(公告)日：2010-06-10
申请号：US12706108
申请日：2010-02-16
申请人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
发明人： Daniel C. Edelstein , Keith Kwong Hon Wong , Chih-Chao Yang , Haining S. Yang
IPC分类号： B32B3/10
CPC分类号： C25D5/02 , Y10T428/24331 , Y10T428/24917
摘要： Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up.
摘要翻译：公开了改进的高宽比电镀金属结构（例如，铜或铜合金互连，例如线的后端（BEOL）或线的中间（MOL）接触）的实施例，其中电镀金属填充材料没有接缝和/或空隙。此外，公开了通过用金属电镀种子层衬里高纵横比开口（例如，高纵横比通孔或沟槽）形成这种电镀金属结构的方法的实施例，然后在其上形成保护层金属电镀种子层的一部分与开口侧壁相邻，使得随后的电镀仅从开口的底表面发生。

10. 发明申请

US20080197499A1 STRUCTURE FOR METAL CAP APPLICATIONS 审中-公开
标题翻译：金属盖应用结构
公开(公告)号：US20080197499A1
公开(公告)日：2008-08-21
申请号：US11675296
申请日：2007-02-15
申请人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
发明人： Chih-Chao Yang , Daniel C. Edelstein , Keith Kwong Hon Wong , Haining Yang
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7684 , H01L21/76826 , H01L21/76834 , H01L21/76849 , H01L21/76885
摘要： An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.
摘要翻译：提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

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