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1. 发明授权

US06175162B1 Semiconductor wafer having a bottom surface protective coating 失效
标题翻译：具有底表面保护涂层的半导体晶片
公开(公告)号：US06175162B1
公开(公告)日：2001-01-16
申请号：US09391854
申请日：1999-09-08
申请人： Pai-Hsiang Kao , William Jeffrey Schaefer , Nikhil Vishwanath Kelkar
发明人： Pai-Hsiang Kao , William Jeffrey Schaefer , Nikhil Vishwanath Kelkar
IPC分类号： H01L2328
CPC分类号： H01L23/562 , H01L21/56 , H01L23/3157 , H01L23/544 , H01L2223/54473 , H01L2223/5448 , H01L2224/16 , H01L2224/274 , H01L2924/01068
摘要： Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the protective film without the laser penetrating to the die. In one preferred embodiment, the protective film of the device is a thick film formed by screen printing. In a preferred embodiment, the protective film has a thickness of between about 1.5 and 5 mils. Also, disclosed is a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies. In this embodiment, the method includes providing a plurality of dies on the top surface of the wafer substrate, applying a thick film over the bottom surface of the wafer substrate, adhering the thick film to a mounting tape that is not ultraviolet curable, and dicing the wafer to separate the dies. The thick film reduces chipping along edges of the separated dies.
摘要翻译：公开了一种封装的集成电路器件。该装置包括在模具的第一表面上具有多个电触头的模具和直接粘附在模具背面上的保护膜，保护膜足够厚以允许保护膜的激光标记而不激光穿透去死在一个优选实施例中，装置的保护膜是通过丝网印刷形成的厚膜。在优选的实施方案中，保护膜的厚度为约1.5至5密耳。此外，公开了一种制造具有具有顶表面和底表面以及多个管芯的晶片衬底的半导体晶片的方法。在本实施例中，该方法包括在晶片衬底的顶表面上提供多个管芯，在晶片衬底的底表面上施加厚膜，将厚膜粘附到不可紫外线固化的安装带上，晶片分离模具。厚膜沿着分离的模具的边缘减小了切屑。

2. 再颁专利

USRE38789E1 Semiconductor wafer having a bottom surface protective coating 有权
标题翻译：具有底表面保护涂层的半导体晶片
公开(公告)号：USRE38789E1
公开(公告)日：2005-09-06
申请号：US10022683
申请日：2001-12-17
申请人： Pai-Hsiang Kao , William Jeffrey Schaefer , Nikhil Vishwanath Kelkar
发明人： Pai-Hsiang Kao , William Jeffrey Schaefer , Nikhil Vishwanath Kelkar
IPC分类号： H01L21/56 , H01L23/00 , H01L23/31 , H01L23/544 , H01L23/58
CPC分类号： H01L23/562 , H01L21/56 , H01L23/3157 , H01L23/544 , H01L2223/54473 , H01L2223/5448 , H01L2224/16 , H01L2224/274 , H01L2924/01068
摘要： Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the protective film without the laser penetrating to the die. In one preferred embodiment, the protective film of the device is a thick film formed by screen printing. In a preferred embodiment, the protective film has a thickness of between about 1.5 and 5 mils. Also, disclosed is a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies. In this embodiment, the method includes providing a plurality of dies on the top surface of the wafer substrate, applying a thick film over the bottom surface of the wafer substrate, adhering the thick film to a mounting tape that is not ultraviolet curable, and dicing the wafer to separate the dies. The thick film reduces chipping along edges of the separated dies.
摘要翻译：公开了一种封装的集成电路器件。该装置包括在模具的第一表面上具有多个电触头的模具和直接粘附在模具背面上的保护膜，保护膜足够厚以允许保护膜的激光标记而不激光穿透去死在一个优选实施例中，装置的保护膜是通过丝网印刷形成的厚膜。在优选的实施方案中，保护膜的厚度为约1.5至5密耳。此外，公开了一种制造具有具有顶表面和底表面以及多个管芯的晶片衬底的半导体晶片的方法。在本实施例中，该方法包括在晶片衬底的顶表面上提供多个管芯，在晶片衬底的底表面上施加厚膜，将厚膜粘附到不可紫外线固化的安装带上，晶片分开模具。厚膜沿着分离的模具的边缘减小了切屑。

3. 发明授权

US6075290A Surface mount die: wafer level chip-scale package and process for making the same 失效
公开(公告)号：US6075290A
公开(公告)日：2000-06-13
申请号：US31167
申请日：1998-02-26
申请人： William Jeffrey Schaefer , Pai-Hsiang Kao , Nikhil Vishwanath Kelkar
发明人： William Jeffrey Schaefer , Pai-Hsiang Kao , Nikhil Vishwanath Kelkar
IPC分类号： H01L23/31 , H01L23/485 , H01L23/48
CPC分类号： H01L23/3171 , H01L23/3192 , H01L2224/0401 , H01L2224/05022 , H01L2224/05558 , H01L2224/05572 , H01L2224/13022 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L24/05 , H01L24/13 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/13091 , H01L2924/14
摘要： Disclosed is an IC package. The IC package includes a die having a plurality of conductive pads. A passivation layer is formed over the conductive pads such that the passivation layer has a plurality of passivation vias. Each passivation via is positioned over an associated one of the conductive pads. A resilient protective layer is formed over the passivation layer. The resilient protective layer has a plurality of resilient vias, wherein each resilient via is associated with an associated passivation via. A plurality of under bump pads are in electrical contact with the conductive pads, and each under bump pad is associated with one of the resilient vias. A plurality of contact bumps are formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads. The resilient protective layer is arranged to absorb stresses introduced at the contact bumps when the IC package is attached to an external substrate; the contact bumps are formed from a material that facilitates absorption of stresses by the resilient protective layer, and the resilient protective layer is further arranged to protect the die. In one preferred embodiment, each under bump pad includes a lip that extends over a portion of the resilient layer. In another preferred embodiment, the contact bumps are formed from a eutectic tin-lead alloy. In another embodiment, a circuit board is disclosed. The circuit board includes a substrate having a plurality of board contacts and the IC package as recited above. In this embodiment, the IC package is attached to the substrate such that each of the contact bumps is coupled with an associated one of the board contacts. In a preferred embodiment, the resilient protective layer of the IC package absorbs stresses introduced at the contact bumps such that an underfill layer is not required between the IC package and the substrate.

4. 发明授权

US6023094A Semiconductor wafer having a bottom surface protective coating 失效
标题翻译：具有底表面保护涂层的半导体晶片
公开(公告)号：US6023094A
公开(公告)日：2000-02-08
申请号：US6759
申请日：1998-01-14
申请人： Pai-Hsiang Kao , William Jeffrey Schaefer , Nikhil Vishwanath Kelkar
发明人： Pai-Hsiang Kao , William Jeffrey Schaefer , Nikhil Vishwanath Kelkar
IPC分类号： H01L21/56 , H01L23/00 , H01L23/31 , H01L23/544 , H01L23/58
CPC分类号： H01L23/562 , H01L21/56 , H01L23/3157 , H01L23/544 , H01L2223/54473 , H01L2223/5448 , H01L2224/16 , H01L2224/274 , H01L2924/01068
摘要： Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the protective film without the laser penetrating to the die. In one preferred embodiment, the protective film of the device is a thick film formed by screen printing. In a preferred embodiment, the protective film has a thickness of between about 1.5 and 5 mils. Also, disclosed is a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies. In this embodiment, the method includes providing a plurality of dies on the top surface of the wafer substrate, applying a thick film over the bottom surface of the wafer substrate, adhering the thick film to a mounting tape that is not ultraviolet curable, and dicing the wafer to separate the dies. The thick film reduces chipping along edges of the separated dies.
摘要翻译：公开了一种封装的集成电路器件。该装置包括在模具的第一表面上具有多个电触头的模具和直接粘附在模具背面上的保护膜，保护膜足够厚以允许保护膜的激光标记而不激光穿透去死在一个优选实施例中，装置的保护膜是通过丝网印刷形成的厚膜。在优选的实施方案中，保护膜的厚度为约1.5至5密耳。此外，公开了一种制造具有具有顶表面和底表面以及多个管芯的晶片衬底的半导体晶片的方法。在本实施例中，该方法包括在晶片衬底的顶表面上提供多个管芯，在晶片衬底的底表面上施加厚膜，将厚膜粘附到不可紫外线固化的安装带上，晶片分离模具。厚膜沿着分离的模具的边缘减小了切屑。

5. 发明授权

US07287323B1 Materials and structure for a high reliability BGA connection between LTCC and PB boards 有权
标题翻译： LTCC和PB板之间的高可靠性BGA连接的材料和结构
公开(公告)号：US07287323B1
公开(公告)日：2007-10-30
申请号：US10837015
申请日：2004-04-30
申请人： Michael Richard Ehlert , William Jeffrey Schaefer
发明人： Michael Richard Ehlert , William Jeffrey Schaefer
IPC分类号： H01R12/36 , H05K1/11 , H05K3/40
CPC分类号： H01L23/49827 , H01L23/49816 , H01L23/49822 , H01L2224/0401 , H01L2224/05571 , H01L2224/10126 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K1/113 , H05K3/248 , H05K3/3452 , H05K3/3457 , H05K3/4061 , H05K2201/017 , H05K2201/035 , H05K2201/09909 , Y10T29/49149 , Y10T29/49165 , H01L2924/00012 , H01L2224/05552
摘要： A ceramic circuit structure comprising a plurality of ceramic layers and at least one electronic component embedded within the plurality of ceramic layers. Within a first one of the ceramic layers is a via that passes through the ceramic layer. A contact pad is formed on a surface of the ceramic layer. A barrier cap is formed between the via and the contact pad. A dielectric ring covers a peripheral portion of the contact pad and an adjacent portion of the dielectric material layer surface immediately surrounding the contact pad, such that any solder that is applied to the contact does not contact the peripheral portion of the contact pad or the ceramic material.
摘要翻译：一种陶瓷电路结构，包括多个陶瓷层和至少一个嵌入在所述多个陶瓷层内的电子部件。在第一陶瓷层之中的是通过陶瓷层的通孔。在陶瓷层的表面上形成接触垫。在通孔和接触垫之间形成阻挡帽。介电环覆盖接触焊盘的周边部分和电介质材料层表面的相邻部分，其紧邻围绕接触焊盘，使得施加到接触件的任何焊料不接触接触焊盘或陶瓷的周边部分材料。

6. 发明授权

US06800815B1 Materials and structure for a high reliability bga connection between LTCC and PB boards 有权
标题翻译： LTCC和PB板之间的高可靠性bga连接的材料和结构
公开(公告)号：US06800815B1
公开(公告)日：2004-10-05
申请号：US10051984
申请日：2002-01-15
申请人： Michael Richard Ehlert , William Jeffrey Schaefer
发明人： Michael Richard Ehlert , William Jeffrey Schaefer
IPC分类号： H05K111
CPC分类号： H01L23/49827 , H01L23/49816 , H01L23/49822 , H01L2224/0401 , H01L2224/05571 , H01L2224/10126 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K1/113 , H05K3/248 , H05K3/3452 , H05K3/3457 , H05K3/4061 , H05K2201/017 , H05K2201/035 , H05K2201/09909 , Y10T29/49149 , Y10T29/49165 , H01L2924/00012 , H01L2224/05552
摘要： A ceramic circuit structure comprising a plurality of ceramic layers and at least one electronic component embedded within the plurality of ceramic layers. Within a first one of the ceramic layers is a via that passes through the ceramic layer. A contact pad is formed on a surface of the ceramic layer. A barrier cap is formed between the via and the contact pad. A dielectric ring covers a peripheral portion of the contact pad and an adjacent portion of the dielectric material layer surface immediately surrounding the contact pad, such that any solder that is applied to the contact does not contact the peripheral portion of the contact pad or the ceramic material.
摘要翻译：一种陶瓷电路结构，包括多个陶瓷层和至少一个嵌入在所述多个陶瓷层内的电子部件。在第一陶瓷层之中的是通过陶瓷层的通孔。在陶瓷层的表面上形成接触垫。在通孔和接触垫之间形成阻挡帽。介电环覆盖接触焊盘的周边部分和电介质材料层表面的相邻部分，其紧邻围绕接触焊盘，使得施加到接触件的任何焊料不接触接触焊盘或陶瓷的周边部分材料。

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