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1. 发明申请

US20130055185A1 VERTICAL POWER BUDGETING AND SHIFTING FOR 3D INTEGRATION 有权
标题翻译：用于3D集成的垂直功率投影和移位
公开(公告)号：US20130055185A1
公开(公告)日：2013-02-28
申请号：US13217429
申请日：2011-08-25
申请人： PRADIP BOSE , GARY D. CARPENTER , MICHAEL S. FLOYD , EREN KURSUN , PHILLIP J. RESTLE , MICHAEL R. SCHEUERMANN
发明人： PRADIP BOSE , GARY D. CARPENTER , MICHAEL S. FLOYD , EREN KURSUN , PHILLIP J. RESTLE , MICHAEL R. SCHEUERMANN
IPC分类号： G06F17/50
CPC分类号： H01L23/50 , G06F17/5045 , G06F2217/78 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565
摘要： A method is provided for managing power distribution on a 3D chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.
摘要翻译：提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆栈组件的3D芯片堆叠上的功率分配的方法。至少两个堆叠组件位于不同的层。存储分别具有不同功耗的工作模式。基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性组件。基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。功率约束包括垂直结构电气约束。

2. 发明申请

US20120330803A1 METHOD AND APPARATUS FOR SUPPORTING MEMORY USAGE THROTTLING 失效
标题翻译：支持记忆使用的方法和装置
公开(公告)号：US20120330803A1
公开(公告)日：2012-12-27
申请号：US13166054
申请日：2011-06-22
申请人： MICHAEL S. FLOYD , GUY L. GUTHRIE , KARTHICK RAJAMANI , GREGORY S. STILL , JEFFREY A. STUECHELI , MALCOLM S. WARE
发明人： MICHAEL S. FLOYD , GUY L. GUTHRIE , KARTHICK RAJAMANI , GREGORY S. STILL , JEFFREY A. STUECHELI , MALCOLM S. WARE
IPC分类号： G06Q30/00 , G06F12/08
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译：公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。

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