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1. 发明授权

US08874893B2 Effect translation and assessment among microarchitecture components 有权
标题翻译：微架构组件之间的效果翻译和评估
公开(公告)号：US08874893B2
公开(公告)日：2014-10-28
申请号：US13429587
申请日：2012-03-26
申请人： Bulent Abali , Michael S. Floyd , Eren Kursun
发明人： Bulent Abali , Michael S. Floyd , Eren Kursun
IPC分类号： G06F9/00 , G06F1/00 , G06F1/32 , G06F15/00 , G06F3/00
CPC分类号： G06F11/3024 , G06F11/3058 , G06F11/3062 , G06F11/3409 , G06F11/3433 , G06F11/348 , G06F2209/501 , G06F2209/508
摘要： Awareness of the relationships among the operating parameters for an individual core and among cores allows dynamic and intelligent management of the multi-core system. The relationships among operating parameters and cores, which can be somewhat opaque, are established with design-time simulations, and adapted with run time data collected from operation of the multi-core system. The relationships are expressed with functions that translate between operating parameters, between different cores, and between operating parameters of different cores. These functions are embodied in circuitry built into the multi-core system. The circuitry will be referred to hereinafter as a translator unit. The translator unit traverses the complex relational dependencies among multiple operating parameters and multiple cores, and determines an outcome with respect to one or more constraints corresponding to those operating parameters and cores.
摘要翻译：意识到单个核心和核心的运行参数之间的关系允许多核系统的动态和智能管理。可以通过设计时模拟建立操作参数和核心之间的关系，这些关系可能有些不透明，并且适用于从多核系统运行收集的运行时数据。这些关系用转换操作参数，不同内核之间以及不同内核的操作参数之间的函数表示。这些功能体现在内置于多核系统中的电路中。电路在下文中将被称为翻译单元。翻译器单元遍历多个操作参数和多个核心之间的复杂关系依赖关系，并且确定与这些操作参数和核心相对应的一个或多个约束的结果。

2. 发明授权

US08856321B2 System to improve operation of a data center with heterogeneous computing clouds 有权
标题翻译：系统改进了具有异构计算云的数据中心的运行
公开(公告)号：US08856321B2
公开(公告)日：2014-10-07
申请号：US13077578
申请日：2011-03-31
申请人： Madhusudan K. Iyengar , Vinod Kamath , Eren Kursun , Roger R. Schmidt
发明人： Madhusudan K. Iyengar , Vinod Kamath , Eren Kursun , Roger R. Schmidt
IPC分类号： G06F15/16 , G06F15/173 , G06F9/50
CPC分类号： G06F9/5094 , Y02D10/22
摘要： A system to improve operation of a data center with heterogeneous computing clouds may include monitoring components to track data center climate controls and individual heterogeneous computing clouds' operating parameters within the data center. The system may also include a controller that regulates the individual heterogeneous computing clouds and data center climate controls based upon data generated by the monitoring components to improve the operating performance of the individual heterogeneous computing clouds as well as the operating performance of the data center. The system may further include spilling computing clouds to receive excess workload of an individual heterogeneous computing cloud without violating individual heterogeneous computing clouds contracts.
摘要翻译：改进具有异构计算云的数据中心运行的系统可能包括监视组件以跟踪数据中心气候控制和数据中心内的个别异构计算云运行参数。该系统还可以包括控制器，其基于由监视组件生成的数据来调节各个异构计算云和数据中心气候控制，以改善各个异构计算云的操作性能以及数据中心的操作性能。该系统可以进一步包括溢出计算云以接收单个异构计算云的额外的工作量，而不违反个别的异构计算云合同。

3. 发明授权

US08516426B2 Vertical power budgeting and shifting for three-dimensional integration 有权
标题翻译：垂直功率预算和三维一体化转移
公开(公告)号：US08516426B2
公开(公告)日：2013-08-20
申请号：US13217429
申请日：2011-08-25
申请人： Pradip Bose , Gary D. Carpenter , Michael S. Floyd , Eren Kursun , Phillip J. Restle , Michael R. Scheuermann
发明人： Pradip Bose , Gary D. Carpenter , Michael S. Floyd , Eren Kursun , Phillip J. Restle , Michael R. Scheuermann
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： H01L23/50 , G06F17/5045 , G06F2217/78 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06565
摘要： A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.
摘要翻译：提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆叠组件的三维芯片堆叠上的功率分配的方法。至少两个堆叠组件位于不同的层。存储分别具有不同功耗的工作模式。基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性组件。基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。功率约束包括垂直结构电气约束。

4. 发明申请

US20120313647A1 INFRASTRUCTURE FOR PERFORMANCE BASED CHIP-TO-CHIP STACKING 有权
标题翻译：基于性能的芯片到芯片堆叠的基础设施
公开(公告)号：US20120313647A1
公开(公告)日：2012-12-13
申请号：US13156836
申请日：2011-06-09
申请人： GARY DALE CARPENTER , Alan James Drake , Eren Kursun , Phillip John Restle
发明人： GARY DALE CARPENTER , Alan James Drake , Eren Kursun , Phillip John Restle
IPC分类号： G01R27/28
CPC分类号： G11C29/025 , G01R31/2882 , G11C7/10 , G11C29/50012 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method and system for an infrastructure for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A critical path monitor circuit (infrastructure) is configured to launch a signal from a launch point in a first layer, the first layer being a first circuit. The infrastructure is further configured to create an electrical path to a capture point. The signal is launched from the launch point in the first layer. A performance characteristic of the electrical path is measured, resulting in a measurement, wherein the measurement is indicative of a performance of the first layer when stacked with a second layer in a 3D stack without actually stacking the first and the second layers in the 3D stack, the second layer being a second circuit.
摘要翻译：在说明性实施例中提供了用于基于性能的芯片到芯片堆叠的基础设施的方法和系统。关键路径监控电路（基础设施）被配置为从第一层中的发射点发射信号，第一层是第一电路。基础设施还被配置为创建到捕获点的电路径。信号从第一层的发射点发射。测量电路径的性能特征，从而进行测量，其中测量表示当与3D堆叠中的第二层堆叠时的第一层的性能，而不会在3D堆叠中实际堆叠第一层和第二层，第二层是第二电路。

5. 发明申请

US20120284541A1 POWER DELIVERY IN A HETEROGENEOUS 3-D STACKED APPARATUS 有权
标题翻译：在异质三维堆叠设备中的电力输送
公开(公告)号：US20120284541A1
公开(公告)日：2012-11-08
申请号：US13552091
申请日：2012-07-18
申请人： Robert H. Dennard , Eren Kursun
发明人： Robert H. Dennard , Eren Kursun
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , H01L23/642 , H01L25/0657 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , Y10T307/50
摘要： A heterogeneous three-dimensional (3-D) stacked apparatus is provided that includes multiple layers arranged in a stacked configuration with a lower layer configured to receive a board-level voltage and one or more upper layers stacked above the lower layer. The heterogeneous 3-D stacked apparatus also includes multiple tiles per layer, where each tile is designed to receive a separately regulated voltage. The heterogeneous 3-D stacked apparatus additionally includes at least one layer in the one or more upper layers with voltage converters providing the separately regulated voltage converted from the board-level voltage.
摘要翻译：提供了一种不均匀的三维（3-D）层叠装置，其包括以堆叠配置布置的多个层，其中下层被配置为接收板级电压，以及堆叠在下层上方的一个或多个上层。异质三维层叠装置还包括每层多个瓦片，其中每个瓦片被设计成接收单独调节的电压。异质三层堆叠装置还包括在一个或多个上层中的至少一个层，其中电压转换器提供从板级电压转换的单独调节的电压。

6. 发明授权

US08141020B2 Temperature-controlled 3-dimensional bus placement 有权
标题翻译：温控三维总线布置
公开(公告)号：US08141020B2
公开(公告)日：2012-03-20
申请号：US12493599
申请日：2009-06-29
申请人： Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip.
摘要翻译：在包含装置的层和紧邻相邻的装置层之间的层间连通性的同时优化的限制下，在每个含有装置的层内的块放置被优化。对于含有装置的层内的每个功能块，横向热流被计算为横向相邻的功能块。如果侧向热流小于一对相邻功能块的阈值，则在其间布置功能块和/或层间互连结构阵列或者修改层间互连结构阵列。对于每个含设备的层中的所有相邻的功能块对，重复此例程。随后，可以在跨所有含有装置的层的层间连接的同时优化的约束下优化在每个包含装置的层内的块放置。该方法提供了在半导体芯片中的每个含有器件的层中具有足够的横向热流的设计。

7. 发明申请

US20110286190A1 Enhanced Modularity in Heterogeneous 3D Stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US20110286190A1
公开(公告)日：2011-11-24
申请号：US12774223
申请日：2010-05-20
申请人： Eren Kursun , Philip G. Emma , Jude A. Rivers
发明人： Eren Kursun , Philip G. Emma , Jude A. Rivers
IPC分类号： H05K7/02
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.
摘要翻译：异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成元件具有相对于主体层和芯片的平滑表面。

8. 发明授权

US07886172B2 Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management 失效
标题翻译：虚拟化和操作系统级热管理方法和具有虚拟化和操作系统级热管理的多线程处理器
公开(公告)号：US07886172B2
公开(公告)日：2011-02-08
申请号：US11845243
申请日：2007-08-27
申请人： Pradip Bose , Chen-Yong Cher , Hubertus Franke , Hendrik Hamann , Eren Kursun , Alan J. Weger
发明人： Pradip Bose , Chen-Yong Cher , Hubertus Franke , Hendrik Hamann , Eren Kursun , Alan J. Weger
IPC分类号： G06F1/32
CPC分类号： G06F1/206 , G06F9/5027 , G06F9/5094 , Y02D10/22
摘要： A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task execution is monitored for hot tasks and especially for hotspots. Task execution is balanced, thermally, to minimize hot spots. Thermal balancing may include Simultaneous MultiThreading (SMT) heat balancing, chip-level multiprocessors (CMP) heat balancing, deferring execution of identified hot tasks, migrating identified hot tasks from a current core to a colder core, User-specified Core-hopping, and SMT hardware threading.
摘要翻译：一种在诸如具有同时多线程（SMT）的芯片级多处理器（CMP）的集成电路芯片上管理任务执行的程序产品和方法。多个芯片操作单元或内核具有用于以单位监测温度的芯片传感器（温度传感器或计数器）。监视任务执行热任务，特别是热点。任务执行是平衡的，热的，以最小化热点。热平衡可以包括同时多线程（SMT）热平衡，芯片级多处理器（CMP）热平衡，推迟识别的热任务的执行，将识别的热任务从当前核心迁移到较冷核心，用户指定的核心跳跃和 SMT硬件线程。

9. 发明授权

US08677613B2 Enhanced modularity in heterogeneous 3D stacks 有权
标题翻译：在异构3D堆栈中增强模块化
公开(公告)号：US08677613B2
公开(公告)日：2014-03-25
申请号：US12774223
申请日：2010-05-20
申请人： Eren Kursun , Philip G. Emma , Jude A. Rivers
发明人： Eren Kursun , Philip G. Emma , Jude A. Rivers
IPC分类号： H05K3/30
CPC分类号： H01L23/147 , H01L21/4803 , H01L23/13 , H01L23/5382 , H01L23/5389 , H01L25/0652 , H01L25/18 , H01L2225/06575 , H01L2225/06589 , H01L2924/0002 , H01L2924/15311 , H05K3/30 , H05K3/465 , Y10T29/49128 , Y10T29/4913 , Y10T29/49137 , Y10T29/49146 , H01L2924/00
摘要： Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.
摘要翻译：异构三维计算机处理芯片堆栈中的增强的模块化包括制造方法。该方法包括准备主机层并将主机层与栈中的至少一个其他层集成。主体层通过在主体层上形成空腔来制备，用于接收相对于彼此预先配置有非均匀性质的芯片，将芯片设置在主体层上的相应空腔中，以及将芯片连接到空腔的相应表面，从而形成元件具有相对于主体层和芯片的平滑表面。

10. 发明申请

US20130331996A1 Optimizing Heat Transfer in 3-D Chip-Stacks 有权
标题翻译：优化3-D芯片堆中的热传递
公开(公告)号：US20130331996A1
公开(公告)日：2013-12-12
申请号：US13494047
申请日：2012-06-12
申请人： Thomas Brunschwiler , Eren Kursun , Gary W. Maier
发明人： Thomas Brunschwiler , Eren Kursun , Gary W. Maier
IPC分类号： G05D23/00 , G05D7/00
CPC分类号： G06F1/20 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A computer-implemented method, system, and article of manufacture for optimizing heat transfer in a 3-D chip-stack. The method includes the steps of: receiving a heat-removal effectiveness parameter for a plurality of channel-region areas in the chip-stack, receiving at least one of a flow value and temperature value for at least two of the channel-region areas, comparing the received values for different channel-region areas, and adjusting a flow rate of a liquid flowing to at least one of the two channel-region areas based on the heat-removal effectiveness parameter of the channel-region area receiving the adjustment and the results of the comparison step, where at least one step is carried out using a computer device.
摘要翻译：用于优化3-D芯片堆叠中的热传递的计算机实现的方法，系统和制品。该方法包括以下步骤：接收码片堆叠中的多个信道区域区域的散热有效性参数，接收至少两个信道区域区域的流量值和温度值中的至少一个，比较不同通道区域的接收值，并且基于接收调整的通道区域区域的散热效率参数来调节流入两个通道区域区域中的至少一个的液体的流量，比较步骤的结果，其中使用计算机设备执行至少一个步骤。

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