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1. 发明申请

US20190044774A1 CLOCK SYNCHRONIZER TO SYNCHRONIZE A DEVICE CLOCK WITH A CLOCK OF A REMOTE DEVICE 审中-公开
公开(公告)号：US20190044774A1
公开(公告)日：2019-02-07
申请号：US16075330
申请日：2017-01-27
申请人： PANTHRONICS AG
发明人： Jan CROLS , Tomaz FELICIJAN , Jakob JONGSMA , Michael PIEBER , Hamzeh NASSAR
IPC分类号： H04L27/26 , H03L7/18 , H04W56/00 , H03L7/087 , H03L7/099 , H04L7/00
摘要： A device (1)) with an antenna that receives a target carrier signal (3) from a remote target (2) and transmits a device carrier signal (6) modulated with data to communicate data between the device (1) and the target (2), which device (1) comprises: clock extraction means (4) to extract a target clock (5) from the target carrier signal (3); driver means (9) to generate the device carrier signal (6) from a device clock (8); synchronization means (7) to synchronize the frequency and phase of the device clock (8) with the target clock (5), wherein that the synchronization means (7) comprise: time measurement means (10) to measure the phase difference between the target clock (5) and the device clock (8) or an internal device clock (33) related to the device clock (8) and to provide a phase information (φ1,φ2,φ3); measurement control means (20) to initiate a first time measurement that results in a first phase information (φ) and to initiate a second time measurement a fixed time period (ΔT) after the first time measurement that results in a second phase information (φ2); frequency correction means (11) to correct the frequency of the device clock (8) and/or the internal device clock (33) to the frequency of the target clock (5) based on an evaluation of the first phase information (φ) and second phase information (φ2) by evaluation means (21); which measurement control means (20) are built to initiate a third time measurement after the frequency correction of the device clock (8) and/or the internal device clock (33) that results in a third phase information (φ3) evaluated by the evaluation means (21) and corrected by phase correction means (22) which correct the phase of the device clock (8) to the phase of the target clock (5).

2. 发明申请

US20190020378A1 TARGET DETECTION BY RFID READER 审中-公开
公开(公告)号：US20190020378A1
公开(公告)日：2019-01-17
申请号：US16065912
申请日：2016-12-12
申请人： PANTHRONICS AG
发明人： Michael PIEBER , Jakob JONGSMA
IPC分类号： H04B5/00 , G06K7/10 , G06K7/00
摘要： A reader (5) with an antenna (6) that transmits a HF field (10) with a carrier frequency and receives an analog input signal (11) with the antenna (6), which analog input signal (11) may be load modulated with a modulation frequency, and outputs digital data detected in the input signal (11), which reader (5) comprises: a mixer (13, 15) that mixes the input signal (11) with a carrier frequency signal (9, 16) and provides a mixed output signal (14); target detection means (22) to detect the presence of a target in the HF field (10) and to activate processing of the input signal (11) to communicate with the target, wherein target detection means (22) comprise: low-pass filter means (23, 25) to eliminate signal components of the mixed output signal (14) at the modulation frequency and above and to provide a filtered output signal (24); quantification means (32) that quantify the filtered output signal (24) and provide quantified detection data (33); decision means (36) that compare the quantified detection data (33) with a threshold (37) to provide a target detected information (38), while the threshold (37) is set in-between quantified detection data (33) received with and without a target present in the HF field (10).

3. 发明申请

US20220190792A1 WAVE-SHAPING FOR OVER- AND UNDERSHOOT PREVENTION 有权
公开(公告)号：US20220190792A1
公开(公告)日：2022-06-16
申请号：US17502881
申请日：2021-10-15
申请人： Panthronics AG
发明人： Jakob JONGSMA , Michael PIEBER
IPC分类号： H03F3/189 , H01Q1/22
摘要： A transmitter (1; 21) to transmit an amplitude modulated data signal (2) in an RF-Field (3) over the air to a receiver (4) of an RFID communication system (5; 22) which transmitter (1; 21) comprises:
a wave generator (6) to generate a carrier signal (7) with a particular frequency and waveform; a modulation stage (15) to modulate the carrier signal (7) in relation to a data signal to be transmitted; an antenna (11) connected to the modulation stage (15) or wave generator (6) via an amplifier (9) and a matching circuit (10) to transmit the amplitude modulated data signal (2) in the RF-Field (3) over the air, characterized in that the transmitter (1; 21) furthermore comprises: a shape stage (16) connected to the wave generator (6) to select the waveform of the carrier signal (7) depending directly or indirectly on the data signal.

4. 发明申请

US20180331867A1 RECEIVER TO PROCESS A LOAD MODULATED ANALOG INPUT SIGNAL 审中-公开
公开(公告)号：US20180331867A1
公开(公告)日：2018-11-15
申请号：US15775314
申请日：2016-11-04
申请人： PANTHRONICS AG
发明人： Jakob JONGSMA
IPC分类号： H04L27/22
CPC分类号： H04L27/22 , G06K7/0008 , H04B1/30
摘要： A Receiver (17) that receives a load modulated analog input signal (19) and outputs digital data (20) detected in the input signal (19), which receiver (17) comprises: an in-phase mixer (21) that mixes the input signal (19) with an in-phase carrier frequency (22) and provides an in-phase component (23) of the down-converted input signal and a quadrature-phase mixer (24) that mixes the input signal (19) with a quadrature-phase carrier frequency (25) and provides a quadrature-phase component (26) of the down-converted input signal; an amplifier (29, 30) to amplify the in-phase component (23) and the quadrature-phase component (26) of the down-converted input signal; a DC block filter (31) to remove the DC component of the in-phase component (23) and the quadrature-phase component (26), wherein the receiver furthermore comprises: an in-phase correlator (33, 34) and a quadrature-phase correlator (35, 36) for each of the in-phase component (23) and the quadrature-phase component (26) to correlate the in-phase component (23) and the quadrature-component (26) with an in-phase component (37) and a quadrature-phase component (38) of a subcarrier or code clock frequency of the input signal (19); a combiner (41) to combine four output signals (48 to 51) of the two in-phase correlators (33, 34) and the two quadrature-phase correlators (35, 36); a slicer (43) to sample an output signal (42) of the combiner (41) at maximum energy levels to output the digital data (20) detected in the input signal (19).

5. 发明申请

US20180367106A1 HIGH-VOLTAGE DIGITAL POWER AMPLIFIER WITH SINUSIOIDAL OUTPUT FOR RFID 审中-公开
公开(公告)号：US20180367106A1
公开(公告)日：2018-12-20
申请号：US16062419
申请日：2016-12-07
申请人： PANTHRONICS AG
发明人： Jan CROLS , Steven GABRIELS , Jakob JONGSMA
IPC分类号： H03F3/213 , H03F3/195 , H03F3/21 , G06K19/07
CPC分类号： H03F3/213 , G06K19/0723 , H03F3/195 , H03F3/20 , H03F3/211 , H03F3/217 , H03F2200/267 , H03F2200/387 , H03F2200/451 , H03F2200/48 , H03M1/745
摘要： A Digital power amplifier (13) to drive an RFID antenna (10) with a substantial sinusoidal output current (I) which digital power amplifier (13) comprises: an integrated circuit (IC2) with a first transmission output pin (15) and a second transmission output pin (16) to provide an output signal (17); an adaption circuit (14) of discrete components (C2a, C2b) connected to the first and second transmission output pin (15, 16) to adapt the output signal (17) and feed the substantial sinusoidal output current (I) with a transmission resonance frequency to the RFID antenna (10), wherein the integrated circuit (IC2) comprises: a digital control section (19) with a number of N wave-forming contacts (20) to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; a number of N driver blocks (21) each connected with a first contact (22) to one of the wave-forming contacts (20) and a number of N/2 of them connected with a second contact to the first transmission output pin (15) and the other number of N/2 of them connected with their second contact to the second transmission output pin (16), which driver blocks (21) are built to provide increments of the substantial sinusoidal output current (I) to the first and second transmission output pin (15, 16).

6. 发明申请

US20180302124A1 NFC "SPLIT STACK" ARCHITECTURE 审中-公开
公开(公告)号：US20180302124A1
公开(公告)日：2018-10-18
申请号：US15769652
申请日：2016-10-18
申请人： PANTHRONICS AG
发明人： Michael PIEBER , Tomaz FELICIJAN , Jakob JONGSMA
IPC分类号： H04B5/00 , H04L29/06
CPC分类号： H04B5/0031 , H04B5/0056 , H04B5/0062 , H04L67/104 , H04L69/08 , H04W4/80
摘要： A device (5; 16; 26) that processes a Near Field Communication type application which device (5; 16; 26) comprises: a host controller circuit (3; 27) that processes device applications, that use the Near Field Communication type application, and that processes a host driver (7; 28) that communicates based on a first interface protocol (NCI; EMV); a NFC controller circuit (4; 33) that processes a Near Field Communication type contactless interface (6; 35) and a controller driver (11; 32) that interfaces with the host controller circuit (3; 27), wherein the host controller circuit (3; 27) processes a first transmission module (9; 30) that interfaces with the host driver (7; 28) based on the first interface protocol (NCI; EMV) and with the controller driver (11; 32) based on a second interface protocol, which first transmission module (9; 30) furthermore processes substantially all none-time critical and/or memory consuming tasks of the Near Field Communication type application and wherein the NFC controller circuit (4; 33) comprises a second transmission module (12, 34) that processes all time critical tasks for the Near Field Communication type application towards the Near Field Communication type contactless interface (6; 35).

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