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1. 发明授权

US06812741B2 Bidirectional signal transmission circuit and bus system 失效
标题翻译：双向信号传输电路和总线系统
公开(公告)号：US06812741B2
公开(公告)日：2004-11-02
申请号：US10394677
申请日：2003-03-21
申请人： Osamu Shibata , Yoshiyuki Saito , Yukihiro Fukumoto
发明人： Osamu Shibata , Yoshiyuki Saito , Yukihiro Fukumoto
IPC分类号： H03K190175
CPC分类号： H04L25/0292 , G06F13/4086 , H04L5/16 , H04L25/0278 , H04L25/028
摘要： A bidirectional transmission circuit for inputting/outputting a signal from/onto a bidirectional transmission line includes: a transceiver for transmitting/receiving a signal; a first element having an impedance; a second element being a short line; and a switching unit for coupling the transceiver to the bidirectional transmission line via the first element when the transceiver transmits a signal, and coupling the transceiver to the bidirectional transmission line via the second element when the transceiver receives a signal.
摘要翻译：用于从双向传输线路输入/输出信号的双向传输电路包括：用于发送/接收信号的收发器; 具有阻抗的第一元件; 第二个元素是短线; 以及切换单元，用于当收发器发送信号时，经由第一元件将收发器耦合到双向传输线，并且当收发器接收到信号时，将收发器经由第二元件耦合到双向传输线。

2. 发明申请

US20090290274A1 REMOVABLE MEMORY CARD 审中-公开
标题翻译：可拆卸记忆卡
公开(公告)号：US20090290274A1
公开(公告)日：2009-11-26
申请号：US12468475
申请日：2009-05-19
申请人： Hiroshi SUENAGA , Yoshiyuki Saito , Osamu Shibata , Yukihiro Fukumoto
发明人： Hiroshi SUENAGA , Yoshiyuki Saito , Osamu Shibata , Yukihiro Fukumoto
IPC分类号： H02H9/04 , H05K1/02
CPC分类号： G06K19/07743 , G06K19/07732 , G06K19/07735 , H01L2224/16225 , H05K1/0237 , H05K1/0259 , H05K1/112 , H05K1/117 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , H05K2201/10159 , H05K2201/10174 , H05K2201/10674
摘要： According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.
摘要翻译：根据本发明，第一端子的设定高度位置被设定为低于印刷基板的端子形成面上的第二端子的设定高度位置，使得内部电路的保护和传输可以实现高速信号。

3. 发明授权

US06901343B2 MULTILAYER BOARD IN WHICH WIRING OF SIGNAL LINE THAT REQUIRES TAMPER-RESISTANCE IS COVERED BY COMPONENT OR FOIL, DESIGN APPARATUS, METHOD, AND PROGRAM FOR THE MULTILAYER BOARD, AND MEDIUM RECORDING THE PROGRAM 有权
标题翻译：组件或者硬盘所要求的防篡改信号线的多层板，多层板的设计，方法和程序，以及程序的中程记录
公开(公告)号：US06901343B2
公开(公告)日：2005-05-31
申请号：US10029571
申请日：2001-12-20
申请人： Eiji Takahashi , Yukihiro Fukumoto , Yoshiyuki Saito , Osamu Shibata , Shinichi Tanimoto , Takeshi Nakayama
发明人： Eiji Takahashi , Yukihiro Fukumoto , Yoshiyuki Saito , Osamu Shibata , Shinichi Tanimoto , Takeshi Nakayama
IPC分类号： G06F17/50 , H05K1/00 , H05K1/02 , H05K1/11 , H04L9/32
CPC分类号： G06F17/5068 , H05K1/0275 , H05K1/0298 , H05K1/114 , H05K2201/09627 , H05K2201/09772 , H05K2201/10151
摘要： A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.
摘要翻译：在组件101的六层板和连接端子102与元件114的端子115之间的信号线需要防篡改。信号线由外层的箔103，通孔104，第三层上的箔111，通孔105，第四层上的箔112，第106层和第六层上的箔113组成。存在于外层的信号线部分都隐藏在电路元件下面。箔103和通孔104的末端放置在第一层116上的部件101下方，通孔105的端部放置在层116上的部件107的下方，通孔106的端部放置在层116上的部件108的下方，另一端通孔104被放置在第六层121上的部件109的下方，通孔105的另一端被放置在层121上的部件110下方，并且箔113和通孔106的另一端放置在层121上的部件114下方。

4. 发明授权

US06629302B2 Circuit board design aiding apparatus, design aiding method, and storage medium storing design aiding program 有权
标题翻译：电路板设计辅助设备，设计辅助方法和存储设备辅助程序存储介质
公开(公告)号：US06629302B2
公开(公告)日：2003-09-30
申请号：US09746886
申请日：2000-12-22
申请人： Shinji Miura , Yukihiro Fukumoto , Hirokazu Uemura , Yoshiyuki Saito , Hiroshi Ikeda , Takeshi Nakayama , Osamu Shibata , Shinichi Tanimoto
发明人： Shinji Miura , Yukihiro Fukumoto , Hirokazu Uemura , Yoshiyuki Saito , Hiroshi Ikeda , Takeshi Nakayama , Osamu Shibata , Shinichi Tanimoto
IPC分类号： G06F945
CPC分类号： G06F17/5068
摘要： A design aiding apparatus and a method, and a storage medium storing a design aiding program enable the efficient layout design of components in a multilayer wiring board formed by laminating a plurality of wiring layers. The design aiding apparatus includes (a) a first acquiring unit for acquiring information showing a first location in a lamination direction of the wiring layers, (b) a second acquiring unit for acquiring information showing a second location on a two-dimensional plane that is orthogonal to the lamination direction, and (c) a placement unit for generating information showing a space to be occupied when the component is placed in such a manner that a placement reference point of the component coincides with the second location that is on the two-dimensional plane including the first location. According to the above construction, the present invention is capable of aiding layout design of components in the wiring board.
摘要翻译：设计辅助装置和方法以及存储设计辅助程序的存储介质使得能够通过层叠多个布线层而形成的多层布线板中的部件的有效布局设计。设计辅助装置包括：（a）第一获取单元，用于获取表示布线层的层叠方向上的第一位置的信息，（b）第二获取单元，用于获取表示二维平面上的第二位置的信息，与所述层叠方向正交，以及（c）放置单元，用于产生表示当所述部件以所述部件的放置基准点与所述第二位置的所述第二位置一致的方式配置时要占据的空间的信息，包括第一位置的三维平面。根据上述结构，本发明能够帮助布线板中部件的布局设计。

5. 发明授权

US06691296B1 Circuit board design aiding 失效
标题翻译：电路板设计辅助
公开(公告)号：US06691296B1
公开(公告)日：2004-02-10
申请号：US09241946
申请日：1999-02-01
申请人： Takeshi Nakayama , Yukihiro Fukumoto , Yoshiyuki Saito , Hirokazu Uemura
发明人： Takeshi Nakayama , Yukihiro Fukumoto , Yoshiyuki Saito , Hirokazu Uemura
IPC分类号： G06F1750
CPC分类号： H05K3/0005 , G06F17/5036 , G06F17/5072 , G06F17/5077 , H01L2924/15192 , H05K1/0231 , H05K1/0298 , H05K1/115 , H05K2201/10689
摘要： A net detecting unit detects a set of component terminal interconnection information showing a critical net from a component terminal interconnection information list. A conductor detecting unit detects a conductor corresponding to the critical net. A component detecting unit detects two components from the set of component terminal interconnection information. A terminal detecting unit detects a power and/or ground terminal of each of the detected components. A power/ground layer detecting unit detects at least one layer, among power and ground layers, to which the detected power and/or ground terminals are connected. A layer detecting unit specifies a layer, among the detected layers, that is nearest to a signal layer on which the conductor is placed. A prohibition area generating unit generates a via prohibition area on the specified layer. As a result, vias are placed on the specified layer, avoiding the via prohibition area.
摘要翻译：网络检测单元从组件终端互连信息列表检测表示关键网络的一组组件终端互连信息。导体检测单元检测与关键网相对应的导体。分量检测单元从组件端子互连信息的集合中检测两个分量。终端检测单元检测每个检测到的组件的功率和/或接地端子。电源/接地层检测单元检测所连接的检测到的电力和/或接地端子的功率和接地层中的至少一层。层检测单元指定在所检测的层之中最接近放置导体的信号层的层。禁止区域生成单元在指定的层上生成通路禁止区域。结果，通孔被放置在指定的层上，避免了通孔禁止区域。

6. 发明授权

US07233889B2 Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device 有权
标题翻译：用于评估半导体器件的抗噪声性的方法，装置和计算机程序
公开(公告)号：US07233889B2
公开(公告)日：2007-06-19
申请号：US10278507
申请日：2002-10-23
申请人： Eiji Takahashi , Yoshiyuki Saito , Yukihiro Fukumoto , Hiroshi Benno
发明人： Eiji Takahashi , Yoshiyuki Saito , Yukihiro Fukumoto , Hiroshi Benno
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.
摘要翻译：提供了一种评估半导体器件的抗噪声性的方法。包括半导体器件的实际电路由具有并联连接的目标等效电路，噪声源等效电路和外部等效电路的等效电路表示。目标等效电路表示半导体器件。噪声源等效电路表示半导体器件外部的噪声源，并且将噪声提供给目标等效电路。外部等效电路表示半导体器件外部的电路。基于由噪声在目标等效电路中产生的电压或电流来评估噪声抗扰度。以这种方式，可以考虑半导体器件外的电路的影响来评估半导体器件对外来噪声的抗扰性。

7. 发明授权

US07886085B2 Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal 有权
标题翻译：可移动存储设备，相位同步方法，相位同步程序，介质记录和主机终端
公开(公告)号：US07886085B2
公开(公告)日：2011-02-08
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： H04L7/10 , G06F1/12 , H04L7/0008 , H04L7/033 , H04L7/044 , H04L7/046
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译：本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分，主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号，提供一个循环。

8. 发明申请

US20100289534A1 INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION 有权
标题翻译：可以在单端传输和差分传输之间切换的接口电路
公开(公告)号：US20100289534A1
公开(公告)日：2010-11-18
申请号：US12847161
申请日：2010-07-30
申请人： Hiroshi SUENAGA , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
发明人： Hiroshi SUENAGA , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
IPC分类号： H03B1/00
CPC分类号： H04L25/028 , H04L25/0272
摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
摘要翻译：本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。两个驱动电路通过驱动控制电路连接到电源电位。通过选择电路输入输入信号的两个输入信号和反相逻辑信号。根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

9. 发明授权

US07737553B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07737553B2
公开(公告)日：2010-06-15
申请号：US11242955
申请日：2005-10-05
申请人： Osamu Shibata , Yoshiyuki Saito
发明人： Osamu Shibata , Yoshiyuki Saito
IPC分类号： H01L23/52
CPC分类号： H01L23/60 , H01L23/552 , H01L23/66 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/45144 , H01L2224/48011 , H01L2224/48091 , H01L2224/4813 , H01L2224/484 , H01L2224/48599 , H01L2224/4911 , H01L2224/49113 , H01L2224/49174 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01019 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： Fine-pitch first and second bonding pads are formed on a chip along its perimeter. The first bonding pads are formed at the peripheral parts on the chip, while the second bonding pads are formed inside the peripheral parts. An ESD protection circuit is connected to the first bonding pad, and an I/O circuit is connected to the second bonding pad. First and second bonding wires connect the first and second bonding pads to the same package pin, respectively. The second bonding wire is configured to be sufficiently longer than the first bonding wire, regardless of the pitch of the first bonding pads.
摘要翻译：细间距第一和第二接合焊盘沿其周边形成在芯片上。第一接合焊盘形成在芯片的周边部分，而第二接合焊盘形成在周边部分内部。 ESD保护电路连接到第一焊盘，并且I / O电路连接到第二接合焊盘。第一和第二接合线分别将第一和第二接合焊盘连接到相同的封装引脚。第二接合线被配置为比第一接合线充分长，而与第一接合焊盘的间距无关。

10. 发明授权

US09002198B2 Optical transmission system 有权
标题翻译：光传输系统
公开(公告)号：US09002198B2
公开(公告)日：2015-04-07
申请号：US13583102
申请日：2011-10-28
申请人： Tsuyoshi Ikushima , Osamu Shibata , Yoshiyuki Saito
发明人： Tsuyoshi Ikushima , Osamu Shibata , Yoshiyuki Saito
IPC分类号： H04B10/00 , H04B10/07 , H04B10/25
CPC分类号： H04B10/07 , H04B10/2503
摘要： An optical transmission system for optically transmitting information between apparatuses via an optical transmission path. The system includes: a sending unit that emits, to the optical transmission path, excitation light for detecting an inter-apparatus connection via the path; a responding unit that receives the excitation light from the path and emits detection light to the path using light energy of the excitation light; a response receiving unit that receives the detection light from the path and outputs a detection light current; a detecting unit that detects presence/absence of the inter-apparatus connection based on the detection light current; a light signal transmitting unit that emits, to the path, a light signal for optically transmitting the information based on the detection result by the detecting unit; and a light signal receiving unit that receives the light signal from the path.
摘要翻译：一种用于经由光传输路径在设备之间光学传输信息的光传输系统。该系统包括：发送单元，其向光传输路径发射用于检测经由路径的装置间连接的激励光; 响应单元，其从所述路径接收激发光，并且使用所述激发光的光能向所述路径发射检测光; 响应接收单元，其从所述路径接收所述检测光并输出检测光电流; 检测单元，其基于所述检测光电流来检测所述装置间连接的有无; 光信号发送单元，基于所述检测单元的检测结果向所述路径发射用于光信息发送的光信号; 以及从该路径接收光信号的光信号接收单元。

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