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1. 发明授权

US08705637B2 Signal transmission device 有权
标题翻译：信号传输装置
公开(公告)号：US08705637B2
公开(公告)日：2014-04-22
申请号：US13805456
申请日：2012-02-13
申请人： Osamu Shibata , Hiroshi Suenaga
发明人： Osamu Shibata , Hiroshi Suenaga
IPC分类号： H04B3/00
CPC分类号： H04B15/00 , H04L25/0266 , H04L25/0276
摘要： A signal transmission device including: a differential signal transmission unit having two output terminals for outputting a differential signal to a paired signal lines including first and second signal lines; a single-ended signal transmission unit having two output terminals for outputting independent two-channel single-ended signals to the paired signal lines; and a filter unit having first and second common mode filters. One terminal of the differential signal transmission unit and one terminal of the single-ended signal transmission unit are connected to the first signal line via one inductor of the first common mode filter of the filter unit. The other one terminal of the differential signal transmission unit and the other one terminal of the single-ended signal transmission unit are connected to the second signal line via one inductor of the second common mode filter of the filter unit.
摘要翻译：一种信号传输装置，包括：差分信号传输单元，具有两个输出端，用于将差分信号输出到包括第一和第二信号线的成对信号线; 一个单端信号传输单元，具有两个输出端，用于向成对的信号线输出独立的双通道单端信号; 以及具有第一和第二共模滤波器的滤波器单元。差分信号传输单元的一个端子和单端信号传输单元的一个端子通过滤波器单元的第一共模滤波器的一个电感器连接到第一信号线。差分信号传输单元的另一个端子和单端信号传输单元的另一个端子通过滤波器单元的第二共模滤波器的一个电感器连接到第二信号线。

2. 发明授权

US07886085B2 Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal 有权
标题翻译：可移动存储设备，相位同步方法，相位同步程序，介质记录和主机终端
公开(公告)号：US07886085B2
公开(公告)日：2011-02-08
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
IPC分类号： G06F13/00 , G06F3/00
CPC分类号： H04L7/10 , G06F1/12 , H04L7/0008 , H04L7/033 , H04L7/044 , H04L7/046
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译：本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。一种向主机终端发送/接收数据的可移动存储装置，包括：接收用于在主机终端和可移动存储装置之间发送/接收数据的发送/接收时钟的时钟接收部分，主机终端; 相位同步模式生成部，其基于所述发送接收时钟生成相位同步模式，所述相位同步模式用于调整所述主机终端结合的用于从所述可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将所生成的相位同步模式发送到所述主机终端，并且所述相位同步模式包括持续至少两个周期的第一电平信号，以及在所述第一电平信号之后持续的第二电平信号，提供一个循环。

3. 发明申请

US20100289534A1 INTERFACE CIRCUIT THAT CAN SWITCH BETWEEN SINGLE-ENDED TRANSMISSION AND DIFFERENTIAL TRANSMISSION 有权
标题翻译：可以在单端传输和差分传输之间切换的接口电路
公开(公告)号：US20100289534A1
公开(公告)日：2010-11-18
申请号：US12847161
申请日：2010-07-30
申请人： Hiroshi SUENAGA , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
发明人： Hiroshi SUENAGA , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Masayuki Toyama , Kyoko Hirata
IPC分类号： H03B1/00
CPC分类号： H04L25/028 , H04L25/0272
摘要： An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.
摘要翻译：本发明的目的是实现在两个传输系统之间切换的接口电路中的输出级驱动器的面积的减小。接口电路具有两个驱动电路和驱动控制电路，该电路可以在作为电压驱动系统和电流驱动系统的两个驱动系统之间切换。两个驱动电路通过驱动控制电路连接到电源电位。通过选择电路输入输入信号的两个输入信号和反相逻辑信号。根据输入到驱动控制电路的控制信号，接口电路在电压驱动型单端传输系统和电流驱动型差动传输系统之间切换。

4. 发明授权

US08708749B2 High-speed interface connector 有权
标题翻译：高速接口连接器
公开(公告)号：US08708749B2
公开(公告)日：2014-04-29
申请号：US13574863
申请日：2012-02-03
申请人： Hiroshi Suenaga , Yutaka Nakamura , Yukihiro Fukumoto
发明人： Hiroshi Suenaga , Yutaka Nakamura , Yukihiro Fukumoto
IPC分类号： H01R24/00
CPC分类号： H01R13/6461 , H01R12/712
摘要： A high-speed interface connector is used for connecting a cable or a memory card each having a differential transmission system signal pin arrangement including a pair of differential transmission signaling pins that are adjacent to each other and two stable potential pins provided on both sides of the pair of differential transmission signaling pins, the two stable potential pins having potentials different from each other. The connector includes: a first and a second contact terminals for differential transmission respectively connected to the pair of differential transmission signaling pins; and a third and a fourth contact terminals provided on both sides of the first and the second contact terminal, the third contact terminal adjacent to the first contact terminal being connected to one of the two stable potential pins, and the fourth contact terminal adjacent to the second contact terminal having a potential identical to that of the third contact terminal.
摘要翻译：高速接口连接器用于连接电缆或存储卡，每个电缆或存储卡具有差分传输系统信号引脚布置，该差分传输系统信号引脚布置包括彼此相邻的一对差分传输信号引脚和两个稳定的电位引脚，一对差分传输信号引脚，两个稳定的电位引脚具有彼此不同的电位。连接器包括：分别连接到该对差分传输信号引脚的用于差分传输的第一和第二接触端子; 以及设置在第一和第二接触端子的两侧的第三和第四接触端子，与第一接触端子相邻的第三接触端子连接到两个稳定电位引脚之一，以及与第二接触端子相邻的第四接触端子第二接触端子具有与第三接触端子的电位相同的电位。

5. 发明申请

US20090290582A1 SIGNAL TRANSMISSION METHOD, TRANSMISSION/RECEPTION DEVICE, AND COMMUNICATION SYSTEM 有权
标题翻译：信号传输方法，传输/接收设备和通信系统
公开(公告)号：US20090290582A1
公开(公告)日：2009-11-26
申请号：US12295407
申请日：2007-02-20
申请人： Hiroshi Suenaga. , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Noriaki Takeda , Takaharu Yoshida
发明人： Hiroshi Suenaga. , Osamu Shibata , Yoshiyuki Saito , Toru Iwata , Noriaki Takeda , Takaharu Yoshida
IPC分类号： H04L12/56 , H04J3/00
CPC分类号： H04L25/14
摘要： It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.
摘要翻译：本发明的一个目的是抑制由于中断信号的传输引起的数据传输效率的下降。本发明提供了一种信号传输方法，其特征在于，接收侧和发送侧将数据划分成多个数据片段，并通过至少两条传输线发送和接收多个数据片段，其中发送侧首先发送在传输线的第一传输线上的多个数据片段的数据片段，通过第二传输线传输包括标题信息的数据包，具有与第一数据片段相同的位长的第二数据片段，以及页脚信息除了第一传输线之外，并且同步地发送第一数据片段和第二数据片段，并且用于控制发送侧的中断信号在作为间隔的时隙中的从接收侧发送到发送侧在第一传输线上相邻的第一数据片段之间。

6. 发明申请

US20090290274A1 REMOVABLE MEMORY CARD 审中-公开
标题翻译：可拆卸记忆卡
公开(公告)号：US20090290274A1
公开(公告)日：2009-11-26
申请号：US12468475
申请日：2009-05-19
申请人： Hiroshi SUENAGA , Yoshiyuki Saito , Osamu Shibata , Yukihiro Fukumoto
发明人： Hiroshi SUENAGA , Yoshiyuki Saito , Osamu Shibata , Yukihiro Fukumoto
IPC分类号： H02H9/04 , H05K1/02
CPC分类号： G06K19/07743 , G06K19/07732 , G06K19/07735 , H01L2224/16225 , H05K1/0237 , H05K1/0259 , H05K1/112 , H05K1/117 , H05K2201/094 , H05K2201/09736 , H05K2201/09845 , H05K2201/10159 , H05K2201/10174 , H05K2201/10674
摘要： According to the present invention, the setting height position of a first terminal is set to be lower than the setting height position of a second terminal on the terminal formation surface of a printed substrate, so that the protection of an internal circuit and the transmission of a high-speed signal can be both achieved.
摘要翻译：根据本发明，第一端子的设定高度位置被设定为低于印刷基板的端子形成面上的第二端子的设定高度位置，使得内部电路的保护和传输可以实现高速信号。

7. 发明申请

US20090233489A1 HOST DEVICE 有权
标题翻译：主机设备
公开(公告)号：US20090233489A1
公开(公告)日：2009-09-17
申请号：US12402016
申请日：2009-03-11
申请人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
发明人： Osamu Shibata , Hiroshi Suenaga , Yoshiyuki Saito
IPC分类号： H01R24/00
CPC分类号： G06F13/1689
摘要： A card controller receives data from a recording card via a socket. A read clock is transmitted in a main transmission wiring, and the data is transmitted in a data transmission wiring. The read clock is withdrawn from the card controller by an outgoing transmission wiring and retrieved into the card controller by an incoming transmission wiring. A transmission delay amount of the outgoing transmission wiring is equal to that of the main transmission wiring, and a transmission delay amount of the incoming transmission wiring is equal to that of the data transmission wiring. The card controller receives the data in synchronization with the read clock retrieved by the incoming transmission wiring.
摘要翻译：卡控制器通过插座从记录卡接收数据。在主发送配线中发送读时钟，在数据发送配线中发送数据。读出时钟通过输出的传输线从卡控制器中取出，并通过输入的传输线被取回到卡控制器中。输出发送线路的发送延迟量与主发送配线的发送延迟量相同，输入发送配线的发送延迟量与数据发送配线的发送延迟量相同。卡控制器与由输入的传输线路检索的读取时钟同步地接收数据。

8. 发明授权

US07385466B2 Differential transmission circuit and common mode choke coil 失效
标题翻译：差动传输电路和共模扼流线圈
公开(公告)号：US07385466B2
公开(公告)日：2008-06-10
申请号：US11085078
申请日：2005-03-22
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
IPC分类号： H03H7/00 , H04B3/28
CPC分类号： H01F17/06 , H01F2017/0093 , H01F2017/067 , H04L25/0272
摘要： A first transmission line for transmitting a first signal and a second transmission line for transmitting a second signal, which has the reverse phase of the first signal, are connected in series with a common mode choke coil. A third transmission line and fourth transmission line are each connected in series with the common mode choke coil, and transmit the first and second signals. A semiconductor device is connected in series with the third and fourth transmission lines, so as to transmit and receive the first and second signals. One end of a first terminator is connected in parallel with the first transmission line, and the other end is connected to the common mode choke coil. One end of a second terminator is connected in parallel with the second transmission line, and the other end is connected to the common mode choke coil. The noise eliminating capability of the common mode choke coil is increased by means of this structure.
摘要翻译：用于发送第一信号的第一传输线和用于发送具有第一信号的相反相位的第二信号的第二传输线与共模扼流线圈串联连接。第三传输线和第四传输线各自与共模扼流线圈串联连接，并发送第一和第二信号。半导体器件与第三和第四传输线串联连接，以便发送和接收第一和第二信号。第一终端器的一端与第一传输线并联连接，另一端连接到共模扼流线圈。第二终端器的一端与第二传输线并联连接，另一端连接到共模扼流线圈。通过这种结构，增加了共模扼流线圈的噪声消除能力。

9. 发明申请

US20060007052A1 Control device for a plurality of display devices 有权
公开(公告)号：US20060007052A1
公开(公告)日：2006-01-12
申请号：US11136435
申请日：2005-05-25
申请人： Mika Nakamura , Hiroshi Suenaga
发明人： Mika Nakamura , Hiroshi Suenaga
IPC分类号： G09G5/00
CPC分类号： G06F3/1431 , G09G5/18 , G09G2330/021 , G09G2330/025
摘要： A data transfer controller for transferring display data to N individual (where N is an integer, N≧2) display devices is disclosed. The data transfer controller includes a clock signal generating means, and a timing control means. The clock signal generating means generates clock signals. The timing control means adjusts the timing of the vertical synchronization signals included in the display data based on the clock signal for N individual display devices. The timing control means adjusts the timing of the vertical synchronization signals such that no vertical blanking period overlaps any other vertical blanking period, or adjusts the timing of the vertical synchronization signals such that no vertical display period overlaps a vertical display period of another display device among the display data transferred to each display device.

10. 发明授权

US6133170A Low density body 失效
标题翻译：低密度体
公开(公告)号：US6133170A
公开(公告)日：2000-10-17
申请号：US10936
申请日：1998-01-22
申请人： Hiroshi Suenaga , Yukihiro Yoshimura , Hisao Ishikawa
发明人： Hiroshi Suenaga , Yukihiro Yoshimura , Hisao Ishikawa
IPC分类号： D21H11/02 , D21H11/00 , D21H11/18 , D21H13/02 , D21H13/10 , D21H13/24 , D21H13/36 , D21H15/04 , D21H17/03 , D21J3/00 , D02G3/04 , D02G3/08
CPC分类号： D21H15/04 , D21H11/00 , D21H13/02 , D21H13/10 , D21H13/24 , D21H13/36
摘要： A low density body such as a sheet, board or molding usable as a cushioning material, heat-insulating material, sound-absorbing material, filter, low density base paper or the like is provided. The low density body having a density of 0.05 to 0.45 g/cm.sup.3 is prepared by dewatering a slurry containing fine fibers having a bond-reinforcing factor of at least 0.15 and curled fibers having a wet curl factor of 0.4 to 1.0, and drying the resultant product.
摘要翻译：提供了诸如可用作缓冲材料的片材，板或模制品的低密度体，绝热材料，吸声材料，过滤器，低密度原纸等。通过使包含粘合强化系数至少为0.15的细纤维和湿卷曲系数为0.4〜1.0的卷曲纤维的浆料脱水，干燥得到的密度为0.05〜0.45g / cm 3的低密度体产品。

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