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1. 发明申请

US20120140540A1 CHARGE SHARING IN A TCAM ARRAY 有权
标题翻译：充电在TCAM阵列中共享
公开(公告)号：US20120140540A1
公开(公告)日：2012-06-07
申请号：US13233065
申请日：2011-09-15
申请人： Oren AGAM , Avidan AKERIB , Eli EHRMAN , Moshe MEYASSED
发明人： Oren AGAM , Avidan AKERIB , Eli EHRMAN , Moshe MEYASSED
IPC分类号： G11C15/00 , G11C8/00
CPC分类号： G11C15/043 , G11C7/1006 , G11C8/08 , G11C8/10 , G11C11/403
摘要： A memory cell includes a storage capacitor, a read line, and a storage transistor, where the storage transistor is connected to the read line and is subject to activation by a charge in the storage capacitor. An in-memory processor includes a memory array which stores data, and an activation unit to activate at least two cells in a column of the memory array at generally the same time, thereby to generate a Boolean function output of the data of the at least two cells, wherein each of the at least two cells includes at least a storage capacitor, a storage transistor and a read line, where the storage transistor is connected to the read line and subject to activation by a charge in the storage capacitor.
摘要翻译：存储单元包括存储电容器，读取线路和存储晶体管，其中存储晶体管连接到读取线并且通过存储电容器中的电荷进行激活。存储器内存处理器包括存储数据的存储器阵列和激活单元，用于在大致相同的时间激活存储器阵列的列中的至少两个单元，从而生成至少该数据的布尔函数输出两个单元，其中所述至少两个单元中的每一个至少包括存储电容器，存储晶体管和读取线，其中所述存储晶体管连接到所述读取线并通过所述存储电容器中的电荷进行激活。

2. 发明申请

US20090303767A1 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS 有权
标题翻译：用于计算的嵌入式相关部分的内存的系统，方法和装置
公开(公告)号：US20090303767A1
公开(公告)日：2009-12-10
申请号：US12464937
申请日：2009-05-13
申请人： Avidan AKERIB , Eli EHRMAN , Josh MEIR , Moshe MEYASSED , Oren AGAM , Yair ALPERN
发明人： Avidan AKERIB , Eli EHRMAN , Josh MEIR , Moshe MEYASSED , Oren AGAM , Yair ALPERN
IPC分类号： G11C15/00 , G11C7/00 , G06F12/02
CPC分类号： G11C15/00 , G06F9/3879 , G06F15/7821 , G11C7/1006 , G11C11/005
摘要： An integrated circuit device includes a semiconductor substrate and an array of random access memory (RAM) cells, which are arranged on the substrate in first columns and are configured to store data. A computational section in the device includes associative memory cells, which are arranged on the substrate in second columns, which are aligned with respective first columns of the RAM cells and are in communication with the respective first columns so as to receive the data from the array of the RAM cells and to perform an associative computation on the data.
摘要翻译：集成电路器件包括半导体衬底和随机存取存储器（RAM）单元阵列，其被布置在第一列中的衬底上，并被配置为存储数据。设备中的计算部分包括相关存储器单元，其被布置在第二列中的衬底上，其与RAM单元的相应的第一列对齐并且与相应的第一列通信，以便从阵列接收数据并且对数据执行关联计算。

3. 发明申请

US20120243284A1 USING STORAGE CELLS TO PERFORM COMPUTATION 有权
标题翻译：使用储存细胞进行计算
公开(公告)号：US20120243284A1
公开(公告)日：2012-09-27
申请号：US13437955
申请日：2012-04-03
申请人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
发明人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
IPC分类号： G11C15/00
CPC分类号： G11C29/34 , G11C15/043
摘要： A content addressable memory (CAM) unit does not have any in-cell comparator circuitry. The CAM unit includes a memory array, a multiple row decoder, a controller and an output unit. The memory array has storage cells arranged as data rows and complement rows. The multiple row decoder activates more than one row of the memory array at a time and the controller indicates to the multiple row decoder to activate data rows or complement rows as a function of an input pattern to be matched. The output unit indicates which columns generated a signal, the columns matching the pattern.
摘要翻译：内容可寻址存储器（CAM）单元没有任何单元内比较器电路。 CAM单元包括存储器阵列，多行解码器，控制器和输出单元。存储器阵列具有排列成数据行和补码行的存储单元。多行解码器一次激活多于一行存储器阵列，并且控制器向多行解码器指示作为要匹配的输入模式的函数来激活数据行或补码行。输出单元指示哪些列生成信号，列与模式匹配。

4. 发明申请

US20120243283A1 USING STORAGE CELLS TO PERFORM COMPUTATION 有权
标题翻译：使用储存细胞进行计算
公开(公告)号：US20120243283A1
公开(公告)日：2012-09-27
申请号：US13437956
申请日：2012-04-03
申请人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
发明人： Avidan AKERIB , Oren AGAM , Eli EHRMAN , Moshe MEYASSED
IPC分类号： G11C15/00
CPC分类号： G11C29/34 , G11C15/043
摘要： A method includes activating at least two rows of pure memory cells and reading at least one column of activated the memory cells, the reading generating a binary function of data stored in the activated memory cells.
摘要翻译：一种方法包括激活至少两行纯存储器单元并读取激活的存储器单元的至少一列，该读取产生存储在激活的存储单元中的数据的二进制函数。

5. 发明申请

US20100164972A1 SYSTEM, METHOD AND APPARATUS FOR MEMORY WITH EMBEDDED ASSOCIATIVE SECTION FOR COMPUTATIONS 有权
标题翻译：用于计算的嵌入式相关部分的内存的系统，方法和装置
公开(公告)号：US20100164972A1
公开(公告)日：2010-07-01
申请号：US12650604
申请日：2009-12-31
申请人： Avidan AKERIB , Eli EHRMAN , Moshe MEYASSED , Oren AGAM
发明人： Avidan AKERIB , Eli EHRMAN , Moshe MEYASSED , Oren AGAM
IPC分类号： G09G5/36
CPC分类号： G11C7/1006 , G09G5/06 , G09G5/393
摘要： A system and method for data processing, the method includes: storing input data words in a row-wise manner in a memory that comprises multiple memory cells arranged in rows and columns; and transposing multiple data words by performing a sequence of shift operations and associative operations; wherein an associative operation comprises comparing in parallel multiple columns of associative memory cells to at least one comparand; and storing transposed data words in the memory.
摘要翻译：一种用于数据处理的系统和方法，所述方法包括：以行方式将输入数据字存储在包括以行和列排列的多个存储单元的存储器中; 以及通过执行移位操作和关联操作的顺序来转置多个数据字; 其中关联操作包括将多个相关联存储器单元并行至少一个比较; 并将转置的数据字存储在存储器中。

6. 发明申请

US20120311404A1 LOW DENSITY PARITY CHECK DECODER 有权
标题翻译：低密度奇偶校验解码器
公开(公告)号：US20120311404A1
公开(公告)日：2012-12-06
申请号：US13483290
申请日：2012-05-30
申请人： Avidan AKERIB
发明人： Avidan AKERIB
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1122 , G11C15/00 , H03M13/1137 , H03M13/114 , H03M13/1165
摘要： An error correction code decoder comprising a computational memory array having at least a variable node section and a check node section, said computational memory array comprising a plurality of computational memory cells, each cell capable of storing at least one bit of memory and of performing operations at least on said bit and each cell implementing one node; and a controller to instruct said computational memory to perform said operations and to write the results of computations on a block of variable nodes into its associated set of blocks of check nodes and to write the results of computations on a block of check nodes into its associated set of blocks of variable nodes.
摘要翻译：一种纠错码解码器，包括具有至少可变节点部分和校验节点部分的计算存储器阵列，所述计算存储器阵列包括多个计算存储器单元，每个单元能够存储至少一个位的存储器和执行操作至少在所述位和每个单元上实现一个节点; 以及控制器，用于指示所述计算存储器执行所述操作并且将可变节点块的计算结果写入其相关联的校验节点块中，并将计算结果写入到相关联的校验节点块中变量节点块集合。

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