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1. 发明授权

US08762626B2 Data modification based on matching bit patterns 有权
标题翻译：基于匹配位模式的数据修改
公开(公告)号：US08762626B2
公开(公告)日：2014-06-24
申请号：US13272648
申请日：2011-10-13
申请人： Omprakash Bisen , Abdulla Pichen
发明人： Omprakash Bisen , Abdulla Pichen
IPC分类号： G06F12/00 , G06F12/02 , G06F11/10 , G11C11/56 , G11C29/42 , G11C16/04
CPC分类号： G06F12/0246 , G06F11/1072 , G06F2212/7201 , G11C11/5628 , G11C16/0483 , G11C2211/5647
摘要： A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.
摘要翻译：数据存储装置包括存储器和控制器。控制器被配置为识别与第一组位模式中的任何位模式匹配的位组。比特组中的每一个包括要存储在存储器中的第一数据的第一位，第二数据的第二位和第三数据的第三位。响应于确定所识别的组的计数超过阈值，控制器被配置为改变第一数据的多个比特。改变第一数据的多个位减少与第一组位模式中的任何位模式相匹配的位组组的数量。

2. 发明授权

US08069403B2 Majority voting logic circuit for dual bus width 有权
标题翻译：双总线宽度多数投票逻辑电路
公开(公告)号：US08069403B2
公开(公告)日：2011-11-29
申请号：US12166174
申请日：2008-07-01
申请人： Omprakash Bisen , Karthikeyan Ramamurthi , Hima Bindu
发明人： Omprakash Bisen , Karthikeyan Ramamurthi , Hima Bindu
IPC分类号： H03M7/00
CPC分类号： G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.
摘要翻译：呈现用于确定是否反转总线的电路，例如可操作具有多个宽度的数据总线。电路包括可以接收总线的当前值和下一个值的比较电路，并且单独地比较总线上的位的当前值和下一个值，以确定这些值是否已改变。投票电路接收这些确定的结果，并且还接收总线正在操作的宽度的指示。然后，投票电路基于是否已经改变的数据上的比特数超过取决于总线宽度的指示的值来确定总线反转值。

3. 发明授权

US09223649B2 System and method of sending correction data to a buffer of a non-volatile memory 有权
标题翻译：将校正数据发送到非易失性存储器的缓冲器的系统和方法
公开(公告)号：US09223649B2
公开(公告)日：2015-12-29
申请号：US13423900
申请日：2012-03-19
申请人： Omprakash Bisen
发明人： Omprakash Bisen
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1048
摘要： A method and apparatus for receiving data from a buffer of a non-volatile memory is described. An error correction coding (ECC) operation is initiated at a controller to correct bit errors in the data. Correction data is sent from the controller to the buffer of the non-volatile memory to correct the bit errors in the data; the correction data may correspond to a portion of the data in the buffer.
摘要翻译：描述了用于从非易失性存储器的缓冲器接收数据的方法和装置。在控制器处启动纠错编码（ECC）操作以校正数据中的位错误。校正数据从控制器发送到非易失性存储器的缓冲器，以纠正数据中的位错误; 校正数据可以对应于缓冲器中的一部分数据。

4. 发明授权

US08917559B2 Multiple write operations without intervening erase 有权
标题翻译：多次写入操作，无需中间擦除
公开(公告)号：US08917559B2
公开(公告)日：2014-12-23
申请号：US13465351
申请日：2012-05-07
申请人： Omprakash Bisen
发明人： Omprakash Bisen
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C17/146 , G11C2211/5641
摘要： A method may be performed by a data storage device and includes writing first data to a group of storage elements. Each particular storage element of the group of storage elements is assigned to a particular state of a first set of states based on a first data value to be stored in the particular storage element. The method also includes overwriting the first data in the group of storage elements with second data. Each particular storage element of the group of storage elements is assigned to a particular state of a second set of states based on a second data value to be stored in the particular storage element. At least one state is included in the first set of states and is excluded from the second set of states.
摘要翻译：方法可以由数据存储装置执行，并且包括将第一数据写入一组存储元件。基于要存储在特定存储元件中的第一数据值，将该组存储元件的每个特定存储元件分配给第一组状态的特定状态。该方法还包括用第二数据重写存储元件组中的第一数据。基于要存储在特定存储元件中的第二数据值，将该组存储元件的每个特定存储元件分配给第二组状态的特定状态。至少一个状态被包括在第一组状态中，并且被排除在第二组状态之外。

5. 发明申请

US20100005373A1 Majority Voting Logic Circuit for Dual Bus Width 有权
标题翻译：双总线宽度的多数投票逻辑电路
公开(公告)号：US20100005373A1
公开(公告)日：2010-01-07
申请号：US12166174
申请日：2008-07-01
申请人： Omprakash Bisen , Karthikeyan Ramamurthi , Hima Bindu
发明人： Omprakash Bisen , Karthikeyan Ramamurthi , Hima Bindu
IPC分类号： G06F11/08
CPC分类号： G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： A circuit is presented for determining whether or not to invert a bus, for example a data bus that is operable having multiple widths. The circuit includes comparison circuitry that can receive both the current and next values for the bus and individually compare the current and next values of the bits on the bus to determine whether these have changed. A voting circuit receives the result of these determinations and also receives an indication of width with which the bus is being operated. The voting circuit then determines a bus inversion values based upon whether the number of bits on the data that have changed exceed a value that depends upon the indication of bus width.
摘要翻译：呈现用于确定是否反转总线的电路，例如可操作具有多个宽度的数据总线。电路包括可以接收总线的当前值和下一个值的比较电路，并且单独地比较总线上的位的当前值和下一个值，以确定这些值是否已改变。投票电路接收这些确定的结果，并且还接收总线正在操作的宽度的指示。然后，投票电路基于是否已经改变的数据上的比特数超过取决于总线宽度的指示的值来确定总线反转值。

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